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| -rwxr-xr-x | testsuite/examples/test-ecp5_versa/testsuite.sh | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/testsuite/examples/test-ecp5_versa/testsuite.sh b/testsuite/examples/test-ecp5_versa/testsuite.sh new file mode 100755 index 0000000..44dac88 --- /dev/null +++ b/testsuite/examples/test-ecp5_versa/testsuite.sh @@ -0,0 +1,25 @@ +#!/bin/sh + +topdir=../.. +. $topdir/testenv.sh + +top=../../.. +src=$top/examples/ecp5_versa + +VHDL_SYN_FILES="$src/versa_ecp5_top.vhdl \ + $src/pll_mac.vhd \ + $src/soc_iomap_pkg.vhdl \ + $src/uart.vhdl \ + $src/uart_tx.vhdl \ + $src/uart_rx.vhdl \ + $src/fifobuf.vhdl" + +VERILOG_FILES="\ + $top/library/wrapper/primitives.v \ + $top/library/wrapper/wrapper.v \ + $top/library/wrapper/bram.v +" + +FREQ=25000000 + +run_yosys -p "ghdl -gCLK_FREQUENCY=$FREQ --work=ecp5um $top/library/ecp5u/components.vhdl --work=work $VHDL_SYN_FILES -e; read_verilog $VERILOG_FILES; synth_ecp5 -top versa_ecp5_top -json top_ecp5_top.json" -l report.txt -q |