2 files changed, 48 insertions, 0 deletions
diff --git a/testsuite/ghdl-issues/issue1682/testsuite.sh b/testsuite/ghdl-issues/issue1682/testsuite.sh
new file mode 100755
index 0000000..99f2d5c
--- /dev/null
+++ b/testsuite/ghdl-issues/issue1682/testsuite.sh
@@ -0,0 +1,10 @@
+#!/bin/sh
+
+topdir=../..
+. $topdir/testenv.sh
+
+run_yosys -q -p "ghdl --std=08 top.vhdl -e; write_verilog exp.v"
+fgrep 'loc = "13"' exp.v > /dev/null
+
+clean
+echo OK
diff --git a/testsuite/ghdl-issues/issue1682/top.vhdl b/testsuite/ghdl-issues/issue1682/top.vhdl
new file mode 100644
index 0000000..2422dc9
--- /dev/null
+++ b/testsuite/ghdl-issues/issue1682/top.vhdl
@@ -0,0 +1,38 @@
+library ieee ;
+context ieee.ieee_std_context;
+
+--use work.components.all;
+
+entity top is
+  port (
+    pin1: out std_logic
+  );
+
+  attribute LOC: string;
+  attribute LOC of pin1: signal is "13";
+end;
+
+architecture arch of top is
+  signal clk: std_logic;
+  signal led_timer: unsigned(23 downto 0) := (others=>'0');
+begin
+
+--  internal_oscillator_inst: OSCH
+--  generic map (
+--    NOM_FREQ => "16.63"
+--  )
+--  port map (
+--    STDBY => '0',
+--    OSC => clk
+--  );
+
+  process(clk)
+  begin
+    if rising_edge(clk) then
+      led_timer <= led_timer + 1;
+    end if;
+  end process;
+
+  pin1 <= led_timer(led_timer'left);
+
+end;