4 files changed, 70 insertions, 0 deletions
diff --git a/testsuite/examples/blackbox/blackbox1.vhdl b/testsuite/examples/blackbox/blackbox1.vhdl
new file mode 100644
index 0000000..fed6d0b
--- /dev/null
+++ b/testsuite/examples/blackbox/blackbox1.vhdl
@@ -0,0 +1,18 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity blackbox1 is
+  port (a, b : std_logic;
+        o : out std_logic);
+end blackbox1;
+
+architecture behav of blackbox1 is
+  component my_blackbox is
+    port (a, b : std_logic;
+          o : out std_logic);
+  end component;
+begin
+  inst: my_blackbox
+    port map (a => a, b => b, o => o);
+end behav;
+
diff --git a/testsuite/examples/blackbox/blackbox2.vhdl b/testsuite/examples/blackbox/blackbox2.vhdl
new file mode 100644
index 0000000..656fe22
--- /dev/null
+++ b/testsuite/examples/blackbox/blackbox2.vhdl
@@ -0,0 +1,18 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity blackbox2 is
+  port (a, b : std_logic;
+        o : out std_logic);
+end;
+
+architecture behav of blackbox2 is
+  component my_blackbox is
+    port (a, b : std_logic;
+          \OUT\ : out std_logic);
+  end component;
+begin
+  inst: my_blackbox
+    port map (a => a, b => b, \OUT\ => o);
+end behav;
+
diff --git a/testsuite/examples/blackbox/blackbox3.vhdl b/testsuite/examples/blackbox/blackbox3.vhdl
new file mode 100644
index 0000000..a506df0
--- /dev/null
+++ b/testsuite/examples/blackbox/blackbox3.vhdl
@@ -0,0 +1,18 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity blackbox3 is
+  port (a, b : std_logic;
+        o : out std_logic);
+end;
+
+architecture behav of blackbox3 is
+  component \lib__cell__box2.3\ is
+    port (a, b : std_logic;
+          \OUT\ : out std_logic);
+  end component;
+begin
+  inst: \lib__cell__box2.3\
+    port map (a => a, b => b, \OUT\ => o);
+end behav;
+
diff --git a/testsuite/examples/blackbox/testsuite.sh b/testsuite/examples/blackbox/testsuite.sh
new file mode 100755
index 0000000..35322f2
--- /dev/null
+++ b/testsuite/examples/blackbox/testsuite.sh
@@ -0,0 +1,16 @@
+#!/bin/sh
+
+topdir=../..
+. $topdir/testenv.sh
+
+run_yosys -q -p "ghdl blackbox1.vhdl -e; write_verilog blackbox1.v"
+fgrep -q "my_blackbox" blackbox1.v
+
+run_yosys -q -p "ghdl blackbox2.vhdl -e; write_verilog blackbox2.v"
+fgrep -q ".OUT(" blackbox2.v
+
+run_yosys -q -p "ghdl blackbox3.vhdl -e; write_verilog blackbox3.v"
+fgrep -q "\lib__cell__box2.3 " blackbox3.v
+
+clean
+echo OK