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+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity counters_3 is
+ port(C, ALOAD : in std_logic;
+ D : in std_logic_vector(3 downto 0);
+ Q : out std_logic_vector(3 downto 0));
+end counters_3;
+
+architecture archi of counters_3 is
+ signal tmp: std_logic_vector(3 downto 0);
+begin
+ process (C, ALOAD, D)
+ begin
+ if (ALOAD='1') then
+ tmp <= D;
+ elsif (C'event and C='1') then
+ tmp <= tmp + 1;
+ end if;
+ end process;
+
+ Q <= tmp;
+
+end archi;