| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Fix for #4: a signal is not always the output of a gate. | Tristan Gingold | 2017-02-13 | 1 | -4/+6 |
| * | Add sources for yosys. | Tristan Gingold | 2017-02-02 | 2 | -0/+389 |
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index : iCE40/ghdl-yosys-plugin | |
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