| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Added proper components.vhdl with uppercase symbols | Martin | 2021-09-15 | 1 | -4243/+4243 |
| * | Fix mult18x18d component to match yosys verilog | JulianKemmerer | 2020-12-19 | 1 | -260/+260 |
| * | Adjust ecp5_versa tests. Wrappers for verilog modules are not needed anymore. | Tristan Gingold | 2020-03-31 | 1 | -60/+60 |
| * | Added ECP5 example for Lattice versa devkit (#85) | Martin | 2020-02-14 | 1 | -0/+4967 |
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index : iCE40/ghdl-yosys-plugin | |
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