| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Fix mult18x18d component to match yosys verilog | JulianKemmerer | 2020-12-19 | 1 | -260/+260 |
| * | Adjust ecp5_versa tests. Wrappers for verilog modules are not needed anymore. | Tristan Gingold | 2020-03-31 | 2 | -61/+61 |
| * | Added ECP5 example for Lattice versa devkit (#85) | Martin | 2020-02-14 | 5 | -0/+5101 |
 |
index : iCE40/ghdl-yosys-plugin | |
| [no description] |
| aboutsummaryrefslogtreecommitdiffstats |