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-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.8.0.115.3
-- Module Version: 5.7
--/usr/local/diamond/3.8_x64/ispfpga/bin/lin64/scuba -w -n pll_mac -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00g -type pll -fin 100.00 -fclkop 125 -fclkop_tol 0.0 -fclkos 25 -fclkos_tol 0.0 -phases 0 -fclkos2 50 -fclkos2_tol 0.0 -phases2 0 -fclkos3 75 -fclkos3_tol 0.0 -phases3 0 -phase_cntl STATIC -lock -fb_mode 1 -fdc /home/strubi/src/masocist/syn/lattice/versaECP5G/ipcores/pll/pll_mac/pll_mac.fdc
-- Wed May 10 17:35:30 2017
library IEEE;
use IEEE.std_logic_1164.all;
library ecp5um;
use ecp5um.components.all;
entity pll_mac is
port (
CLKI: in std_logic;
CLKOP: out std_logic;
CLKOS: out std_logic;
CLKOS2: out std_logic;
CLKOS3: out std_logic;
LOCK: out std_logic);
end pll_mac;
architecture Structure of pll_mac is
-- internal signal declarations
signal REFCLK: std_logic;
signal CLKOS3_t: std_logic;
signal CLKOS2_t: std_logic;
signal CLKOS_t: std_logic;
signal CLKOP_t: std_logic;
signal scuba_vhi: std_logic;
signal scuba_vlo: std_logic;
attribute FREQUENCY_PIN_CLKOS3 : string;
attribute FREQUENCY_PIN_CLKOS2 : string;
attribute FREQUENCY_PIN_CLKOS : string;
attribute FREQUENCY_PIN_CLKOP : string;
attribute FREQUENCY_PIN_CLKI : string;
attribute ICP_CURRENT : string;
attribute LPF_RESISTOR : string;
attribute FREQUENCY_PIN_CLKOS3 of PLLInst_0 : label is "75.000000";
attribute FREQUENCY_PIN_CLKOS2 of PLLInst_0 : label is "50.000000";
attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "25.000000";
attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "125.000000";
attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "100.000000";
attribute ICP_CURRENT of PLLInst_0 : label is "7";
attribute LPF_RESISTOR of PLLInst_0 : label is "16";
attribute syn_keep : boolean;
attribute NGD_DRC_MASK : integer;
attribute NGD_DRC_MASK of Structure : architecture is 1;
begin
-- component instantiation statements
scuba_vhi_inst: VHI
port map (Z=>scuba_vhi);
scuba_vlo_inst: VLO
port map (Z=>scuba_vlo);
PLLInst_0: EHXPLLL
generic map (PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED",
STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED",
CLKOS3_FPHASE=> 0, CLKOS3_CPHASE=> 9, CLKOS2_FPHASE=> 0,
CLKOS2_CPHASE=> 14, CLKOS_FPHASE=> 0, CLKOS_CPHASE=> 29,
CLKOP_FPHASE=> 0, CLKOP_CPHASE=> 5, PLL_LOCK_MODE=> 0,
CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "FALLING",
CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "FALLING",
OUTDIVIDER_MUXD=> "DIVD", CLKOS3_ENABLE=> "ENABLED",
OUTDIVIDER_MUXC=> "DIVC", CLKOS2_ENABLE=> "ENABLED",
OUTDIVIDER_MUXB=> "DIVB", CLKOS_ENABLE=> "ENABLED",
OUTDIVIDER_MUXA=> "DIVA", CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 10,
CLKOS2_DIV=> 15, CLKOS_DIV=> 30, CLKOP_DIV=> 6, CLKFB_DIV=> 5,
CLKI_DIV=> 4, FEEDBK_PATH=> "CLKOP")
port map (CLKI=>CLKI, CLKFB=>CLKOP_t, PHASESEL1=>scuba_vlo,
PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo,
PHASESTEP=>scuba_vlo, PHASELOADREG=>scuba_vlo,
STDBY=>scuba_vlo, PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo,
ENCLKOP=>scuba_vlo, ENCLKOS=>scuba_vlo, ENCLKOS2=>scuba_vlo,
ENCLKOS3=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>CLKOS_t,
CLKOS2=>CLKOS2_t, CLKOS3=>CLKOS3_t, LOCK=>LOCK,
INTLOCK=>open, REFCLK=>REFCLK, CLKINTFB=>open);
CLKOS3 <= CLKOS3_t;
CLKOS2 <= CLKOS2_t;
CLKOS <= CLKOS_t;
CLKOP <= CLKOP_t;
end Structure;
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