blob: 9d512b0325ee9cd2f8baa24e37a2a608460c538c (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
|
library ieee;
use ieee.std_logic_1164.all;
entity loop1 is
port (a : std_logic_vector (7 downto 0);
o : out std_logic_vector (15 downto 0));
end;
architecture behav of loop1 is
signal s : std_logic_vector (15 downto 0);
begin
s <= a & s (15 downto 8);
o <= s;
end behav;
|