cell1.vhdl « issue73 « issues « testsuite - iCE40/ghdl-yosys-plugin

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library ieee;
use ieee.std_logic_1164.all;

entity cell1 is
  port (
    O: out std_logic
  );
end entity cell1;

architecture rtl of cell1 is
begin
  O <= '0';
end architecture rtl;