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authorTristan Gingold <tgingold@free.fr>2016-02-13 18:17:21 +0100
committerTristan Gingold <tgingold@free.fr>2016-02-14 13:52:34 +0100
commit03a502169b3a3656018236ec4d4952a3fd4ec880 (patch)
tree1784c7c25db963dce7ac2340c740a428a4ab8ced
parent32d422d2f5d002354aeaf111ce484b6665a5c9d5 (diff)
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simul: more fixes for std_ulogic.
-rw-r--r--src/ghdldrv/ghdllocal.adb10
-rw-r--r--src/vhdl/simulate/execution.adb27
-rw-r--r--src/vhdl/simulate/simulation.adb11
3 files changed, 30 insertions, 18 deletions
diff --git a/src/ghdldrv/ghdllocal.adb b/src/ghdldrv/ghdllocal.adb
index 0072b3724..dfc206649 100644
--- a/src/ghdldrv/ghdllocal.adb
+++ b/src/ghdldrv/ghdllocal.adb
@@ -83,13 +83,21 @@ package body Ghdllocal is
raise Compilation_Error;
end if;
- if Flags.Flag_Elaborate then
+ if Flags.Flag_Elaborate
+ or else ((Main or Flags.List_All) and then Flags.List_Canon)
+ then
if Flags.Verbose then
Put_Line ("canonicalize " & Disp_Node (Get_Library_Unit (Unit)));
end if;
Canon.Canonicalize (Unit);
+ if (Main or Flags.List_All) and then Flags.List_Canon then
+ Disp_Vhdl.Disp_Vhdl (Unit);
+ end if;
+ end if;
+
+ if Flags.Flag_Elaborate then
if Flag_Create_Default_Config then
Lib := Get_Library_Unit (Unit);
if Get_Kind (Lib) = Iir_Kind_Architecture_Body then
diff --git a/src/vhdl/simulate/execution.adb b/src/vhdl/simulate/execution.adb
index 9c6da7731..78b5e8310 100644
--- a/src/vhdl/simulate/execution.adb
+++ b/src/vhdl/simulate/execution.adb
@@ -1364,7 +1364,7 @@ package body Execution is
begin
for I in Right.Val_Array.V'Range loop
Format (Positive (I)) :=
- Character'Val (Right.Val_Array.V (I).E32);
+ Character'Val (Right.Val_Array.V (I).E8);
end loop;
Format (Format'Last) := ASCII.NUL;
Grt.Vstrings.To_String
@@ -1399,27 +1399,27 @@ package body Execution is
declare
use Grt.Std_Logic_1164;
begin
- Result := Create_E32_Value
+ Result := Create_E8_Value
(Std_Ulogic'Pos
- (Match_Eq_Table (Std_Ulogic'Val (Left.E32),
- Std_Ulogic'Val (Right.E32))));
+ (Match_Eq_Table (Std_Ulogic'Val (Left.E8),
+ Std_Ulogic'Val (Right.E8))));
end;
when Iir_Predefined_Std_Ulogic_Match_Inequality =>
Eval_Right;
declare
use Grt.Std_Logic_1164;
begin
- Result := Create_E32_Value
+ Result := Create_E8_Value
(Std_Ulogic'Pos
- (Not_Table (Match_Eq_Table (Std_Ulogic'Val (Left.E32),
- Std_Ulogic'Val (Right.E32)))));
+ (Not_Table (Match_Eq_Table (Std_Ulogic'Val (Left.E8),
+ Std_Ulogic'Val (Right.E8)))));
end;
when Iir_Predefined_Std_Ulogic_Match_Ordering_Functions =>
Eval_Right;
declare
use Grt.Std_Logic_1164;
- L : constant Std_Ulogic := Std_Ulogic'Val (Left.E32);
- R : constant Std_Ulogic := Std_Ulogic'Val (Right.E32);
+ L : constant Std_Ulogic := Std_Ulogic'Val (Left.E8);
+ R : constant Std_Ulogic := Std_Ulogic'Val (Right.E8);
Res : Std_Ulogic;
begin
Check_Std_Ulogic_Dc (Expr, L);
@@ -1437,7 +1437,7 @@ package body Execution is
when Iir_Predefined_Std_Ulogic_Match_Greater_Equal =>
Res := Not_Table (Match_Lt_Table (L, R));
end case;
- Result := Create_E32_Value (Std_Ulogic'Pos (Res));
+ Result := Create_E8_Value (Std_Ulogic'Pos (Res));
end;
when Iir_Predefined_Std_Ulogic_Array_Match_Equality
@@ -1452,11 +1452,10 @@ package body Execution is
Le, Re : Std_Ulogic;
Has_Match_Err : Boolean;
begin
- Result := Create_E32_Value (Std_Ulogic'Pos ('1'));
Has_Match_Err := False;
for I in Left.Val_Array.V'Range loop
- Le := Std_Ulogic'Val (Left.Val_Array.V (I).E32);
- Re := Std_Ulogic'Val (Right.Val_Array.V (I).E32);
+ Le := Std_Ulogic'Val (Left.Val_Array.V (I).E8);
+ Re := Std_Ulogic'Val (Right.Val_Array.V (I).E8);
if (Le = '-' or Re = '-') and then not Has_Match_Err then
Assert_Std_Ulogic_Dc (Expr);
Has_Match_Err := True;
@@ -1466,7 +1465,7 @@ package body Execution is
if Func = Iir_Predefined_Std_Ulogic_Array_Match_Inequality then
Res := Not_Table (Res);
end if;
- Result := Create_E32_Value (Std_Ulogic'Pos (Res));
+ Result := Create_E8_Value (Std_Ulogic'Pos (Res));
end;
when others =>
diff --git a/src/vhdl/simulate/simulation.adb b/src/vhdl/simulate/simulation.adb
index c33997b7d..728e7b0cb 100644
--- a/src/vhdl/simulate/simulation.adb
+++ b/src/vhdl/simulate/simulation.adb
@@ -1294,6 +1294,11 @@ package body Simulation is
raise Internal_Error;
end if;
Grt.Signals.Ghdl_Signal_Associate_B1 (Port.Sig, Sig.B1);
+ when Iir_Value_E8 =>
+ if Mode = Connect_Source then
+ raise Internal_Error;
+ end if;
+ Grt.Signals.Ghdl_Signal_Associate_E8 (Port.Sig, Sig.E8);
when others =>
raise Internal_Error;
end case;
@@ -1622,7 +1627,7 @@ package body Simulation is
Pfx.Val_Array.V (I), Time);
end loop;
when Iir_Value_Signal =>
- case Val.Kind is
+ case Iir_Value_Scalars (Val.Kind) is
when Iir_Value_I64 =>
Val_Ptr := To_Ghdl_Value_Ptr (Val.I64'Address);
when Iir_Value_E32 =>
@@ -1631,8 +1636,8 @@ package body Simulation is
Val_Ptr := To_Ghdl_Value_Ptr (Val.F64'Address);
when Iir_Value_B1 =>
Val_Ptr := To_Ghdl_Value_Ptr (Val.B1'Address);
- when others =>
- raise Internal_Error;
+ when Iir_Value_E8 =>
+ Val_Ptr := To_Ghdl_Value_Ptr (Val.E8'Address);
end case;
Sig.Sig := Grt.Signals.Ghdl_Create_Delayed_Signal
(Pfx.Sig, Val_Ptr, Time);