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authorTristan Gingold <tgingold@free.fr>2019-11-28 18:39:43 +0100
committerTristan Gingold <tgingold@free.fr>2019-11-28 18:40:28 +0100
commit05a0a9c919e70079e93a2608020f8a1042bb7dc9 (patch)
tree58321ea58611e88f48da0791c98e373d5e1ce658
parent9272b09a4fdac810bdd1a1aedb4d7fcc2604c9e1 (diff)
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testsuite: add test case for #1043
-rw-r--r--testsuite/synth/issue1043/ent.vhdl22
-rwxr-xr-xtestsuite/synth/issue1043/testsuite.sh12
2 files changed, 34 insertions, 0 deletions
diff --git a/testsuite/synth/issue1043/ent.vhdl b/testsuite/synth/issue1043/ent.vhdl
new file mode 100644
index 000000000..0d0b83ea2
--- /dev/null
+++ b/testsuite/synth/issue1043/ent.vhdl
@@ -0,0 +1,22 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ent is
+ generic (
+ g : natural := 8
+ );
+ port (
+ o1 : out std_logic;
+ o2 : out std_logic
+ );
+end;
+
+architecture a of ent is
+ constant x : real := real(g);
+
+ constant a : natural := g;
+ constant y : real := real(a);
+begin
+ o1 <= '1' when integer(x) = 8 else '0';
+ o2 <= '1' when integer(y) = 8 else '0';
+end;
diff --git a/testsuite/synth/issue1043/testsuite.sh b/testsuite/synth/issue1043/testsuite.sh
new file mode 100755
index 000000000..bc454cfda
--- /dev/null
+++ b/testsuite/synth/issue1043/testsuite.sh
@@ -0,0 +1,12 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in ent; do
+ synth $t.vhdl -e $t > syn_$t.vhdl
+ analyze syn_$t.vhdl
+done
+
+clean
+
+echo "Test successful"