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| author | Tristan Gingold <tgingold@free.fr> | 2022-06-27 08:24:50 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-06-27 08:24:50 +0200 |
| commit | 060840d4176d7e5b775616e8a702bd751765c753 (patch) | |
| tree | 168a6e3aadaa41428c40c9411fa4c2c5e87e2b94 | |
| parent | e5e2caa620846928bb85ccc5206375c2b7321a66 (diff) | |
| download | ghdl-060840d4176d7e5b775616e8a702bd751765c753.tar.gz ghdl-060840d4176d7e5b775616e8a702bd751765c753.tar.bz2 ghdl-060840d4176d7e5b775616e8a702bd751765c753.zip | |
synth/netlists-disp_verilog: adjust previous patch. For #2109
| -rw-r--r-- | src/synth/netlists-disp_verilog.adb | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/synth/netlists-disp_verilog.adb b/src/synth/netlists-disp_verilog.adb index 8eb76d332..b2461bf2f 100644 --- a/src/synth/netlists-disp_verilog.adb +++ b/src/synth/netlists-disp_verilog.adb @@ -1150,7 +1150,8 @@ package body Netlists.Disp_Verilog is and then Id in Edge_Module_Id and then not Need_Edge (Inst)) or else (not Flag_Null_Wires - or else Get_Width (Get_Output (Inst, 0)) = 0) + and then Get_Nbr_Outputs (Inst) = 1 + and then Get_Width (Get_Output (Inst, 0)) = 0) then -- Not displayed. null; |