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| author | Tristan Gingold <tgingold@free.fr> | 2019-09-25 08:04:58 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-09-25 08:04:58 +0200 |
| commit | 13fcbfe8a2ef3e027458b88d338909172e6f5133 (patch) | |
| tree | 983c246cfe8c6fbfc3e38edfdcbe05da0473c19b | |
| parent | 3fca9501e16d90cc268b641ae165a22afdacf5e8 (diff) | |
| download | ghdl-13fcbfe8a2ef3e027458b88d338909172e6f5133.tar.gz ghdl-13fcbfe8a2ef3e027458b88d338909172e6f5133.tar.bz2 ghdl-13fcbfe8a2ef3e027458b88d338909172e6f5133.zip | |
synth-disp_vhdl: handle in conversions from bitvector. Fix #940
| -rw-r--r-- | src/synth/synth-disp_vhdl.adb | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/synth/synth-disp_vhdl.adb b/src/synth/synth-disp_vhdl.adb index d801e0fc1..0ea78fc26 100644 --- a/src/synth/synth-disp_vhdl.adb +++ b/src/synth/synth-disp_vhdl.adb @@ -155,6 +155,11 @@ package body Synth.Disp_Vhdl is Put (" (" & Pfx & "'left)"); end if; Put_Line (");"); + elsif Btype = Vhdl.Std_Package.Bit_Vector_Type_Definition then + W := Typ.Vbound.Len; + Disp_In_Lhs (Mname, Off, W, Full); + Put ("to_stdlogicvector (" & Pfx & ")"); + Put_Line (";"); else Error_Kind ("disp_in_converter(arr)", Ptype); end if; |