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author | Tristan Gingold <tgingold@free.fr> | 2017-08-25 05:22:08 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2017-08-25 05:22:08 +0200 |
commit | 14bfd405cc786f8201b9a6f5303fcdbcfdfbb484 (patch) | |
tree | 026e0ee7d6f199b08bf6cdaa7a814c19938287fc | |
parent | cb1a979037ac59a80e09cdcc095871480757859d (diff) | |
download | ghdl-14bfd405cc786f8201b9a6f5303fcdbcfdfbb484.tar.gz ghdl-14bfd405cc786f8201b9a6f5303fcdbcfdfbb484.tar.bz2 ghdl-14bfd405cc786f8201b9a6f5303fcdbcfdfbb484.zip |
Add testcase for #400
-rw-r--r-- | testsuite/gna/issue400/e.vhdl | 17 | ||||
-rwxr-xr-x | testsuite/gna/issue400/testsuite.sh | 11 |
2 files changed, 28 insertions, 0 deletions
diff --git a/testsuite/gna/issue400/e.vhdl b/testsuite/gna/issue400/e.vhdl new file mode 100644 index 000000000..7bebb2168 --- /dev/null +++ b/testsuite/gna/issue400/e.vhdl @@ -0,0 +1,17 @@ +entity e is end entity; +architecture a of e is + type p is protected + function f(a:bit) return boolean; + end protected; + type p is protected body + function f(a:bit) return boolean is begin return a='1'; end function; + end protected body; + shared variable v :p; + component bb1 is port( s :out bit ); end component; + component bb2 is port( s :in boolean ); end component; + signal s1 :boolean; + signal s2 :bit; +begin + i1: component bb1 port map( v.f(s) => s1 ); + i2: component bb2 port map( s => v.f(s2) ); +end architecture; diff --git a/testsuite/gna/issue400/testsuite.sh b/testsuite/gna/issue400/testsuite.sh new file mode 100755 index 000000000..1a4b10413 --- /dev/null +++ b/testsuite/gna/issue400/testsuite.sh @@ -0,0 +1,11 @@ +#! /bin/sh + +. ../../testenv.sh + +export GHDL_STD_FLAGS=--std=08 +analyze e.vhdl +elab_simulate e + +clean + +echo "Test successful" |