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| author | Tristan Gingold <tgingold@free.fr> | 2019-10-12 19:17:07 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-10-13 18:54:23 +0200 |
| commit | 15dd6b468d4f1e83ee0948b54b8892ae1502b74f (patch) | |
| tree | d11fbed2c1a7ba5f712bf2d2fc0fef749b03a0a1 | |
| parent | e31f8827aa700dd69333dd5fc6804a90b5d94742 (diff) | |
| download | ghdl-15dd6b468d4f1e83ee0948b54b8892ae1502b74f.tar.gz ghdl-15dd6b468d4f1e83ee0948b54b8892ae1502b74f.tar.bz2 ghdl-15dd6b468d4f1e83ee0948b54b8892ae1502b74f.zip | |
synth-oper: handle unsigned unsigned mul.
| -rw-r--r-- | src/synth/synth-oper.adb | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/synth/synth-oper.adb b/src/synth/synth-oper.adb index 8f85a8817..04380259b 100644 --- a/src/synth/synth-oper.adb +++ b/src/synth/synth-oper.adb @@ -539,6 +539,19 @@ package body Synth.Oper is return Create_Value_Net (N, Create_Vec_Type_By_Length (W, Left.Typ.Vec_El)); end; + when Iir_Predefined_Ieee_Numeric_Std_Mul_Uns_Uns => + declare + W : constant Width := Left.Typ.W + Right.Typ.W; + L, R : Net; + N : Net; + begin + L := Synth_Uresize (Left, W, Left_Expr); + R := Synth_Uresize (Right, W, Right_Expr); + N := Build_Dyadic (Build_Context, Id_Umul, L, R); + Set_Location (N, Expr); + return Create_Value_Net + (N, Create_Vec_Type_By_Length (W, Left.Typ.Vec_El)); + end; when Iir_Predefined_Ieee_Numeric_Std_Mul_Uns_Nat => declare L : constant Net := Get_Net (Left); |