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author | Tristan Gingold <tgingold@free.fr> | 2019-10-07 18:58:04 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-10-07 18:58:04 +0200 |
commit | 167a6d0c0c9bdcc6381183e4913df7ccab03269e (patch) | |
tree | 0d8b29079de198685f9699bcac68f78b8a8457ff | |
parent | cdda9d783f71a13fa2c828f6b8677f64932f6a6e (diff) | |
download | ghdl-167a6d0c0c9bdcc6381183e4913df7ccab03269e.tar.gz ghdl-167a6d0c0c9bdcc6381183e4913df7ccab03269e.tar.bz2 ghdl-167a6d0c0c9bdcc6381183e4913df7ccab03269e.zip |
vhdl: recognize to_bitvector.
-rw-r--r-- | src/std_names.adb | 1 | ||||
-rw-r--r-- | src/std_names.ads | 7 | ||||
-rw-r--r-- | src/vhdl/vhdl-ieee-std_logic_1164.adb | 153 | ||||
-rw-r--r-- | src/vhdl/vhdl-nodes.ads | 2 |
4 files changed, 79 insertions, 84 deletions
diff --git a/src/std_names.adb b/src/std_names.adb index 9df07bb6d..3338c805d 100644 --- a/src/std_names.adb +++ b/src/std_names.adb @@ -646,6 +646,7 @@ package body Std_Names is Def ("shift_right", Name_Shift_Right); Def ("rotate_left", Name_Rotate_Left); Def ("rotate_right", Name_Rotate_Right); + Def ("to_bitvector", Name_To_Bitvector); Def ("math_real", Name_Math_Real); Def ("ceil", Name_Ceil); Def ("log2", Name_Log2); diff --git a/src/std_names.ads b/src/std_names.ads index da13ace61..ff489c8bf 100644 --- a/src/std_names.ads +++ b/src/std_names.ads @@ -727,9 +727,10 @@ package Std_Names is Name_Shift_Right : constant Name_Id := Name_First_Ieee + 025; Name_Rotate_Left : constant Name_Id := Name_First_Ieee + 026; Name_Rotate_Right : constant Name_Id := Name_First_Ieee + 027; - Name_Math_Real : constant Name_Id := Name_First_Ieee + 028; - Name_Ceil : constant Name_Id := Name_First_Ieee + 029; - Name_Log2 : constant Name_Id := Name_First_Ieee + 030; + Name_To_Bitvector : constant Name_Id := Name_First_Ieee + 028; + Name_Math_Real : constant Name_Id := Name_First_Ieee + 029; + Name_Ceil : constant Name_Id := Name_First_Ieee + 030; + Name_Log2 : constant Name_Id := Name_First_Ieee + 031; Name_Last_Ieee : constant Name_Id := Name_Log2; -- Verilog Directives. diff --git a/src/vhdl/vhdl-ieee-std_logic_1164.adb b/src/vhdl/vhdl-ieee-std_logic_1164.adb index 7ea7da787..80c4c6ece 100644 --- a/src/vhdl/vhdl-ieee-std_logic_1164.adb +++ b/src/vhdl/vhdl-ieee-std_logic_1164.adb @@ -122,6 +122,7 @@ package body Vhdl.Ieee.Std_Logic_1164 is Decl : Iir; Def : Iir; + Predefined : Iir_Predefined_Functions; begin Std_Logic_1164_Pkg := Pkg; @@ -224,88 +225,78 @@ package body Vhdl.Ieee.Std_Logic_1164 is exit when Decl = Null_Iir; if Get_Kind (Decl) = Iir_Kind_Function_Declaration then - if Get_Identifier (Decl) = Name_Rising_Edge then - Rising_Edge := Decl; - elsif Get_Identifier (Decl) = Name_Falling_Edge then - Falling_Edge := Decl; - elsif Is_Scalar_Scalar_Function (Decl) then - declare - Predefined : Iir_Predefined_Functions; - begin - case Get_Identifier (Decl) is - when Name_And => - Predefined := Iir_Predefined_Ieee_1164_Scalar_And; - when Name_Nand => - Predefined := Iir_Predefined_Ieee_1164_Scalar_Nand; - when Name_Or => - Predefined := Iir_Predefined_Ieee_1164_Scalar_Or; - when Name_Nor => - Predefined := Iir_Predefined_Ieee_1164_Scalar_Nor; - when Name_Xor => - Predefined := Iir_Predefined_Ieee_1164_Scalar_Xor; - when Name_Xnor => - Predefined := Iir_Predefined_Ieee_1164_Scalar_Xnor; - when others => - Predefined := Iir_Predefined_None; - end case; + case Get_Identifier (Decl) is + when Name_Rising_Edge => + Rising_Edge := Decl; + when Name_Falling_Edge => + Falling_Edge := Decl; + when Name_To_Bitvector => + Predefined := Iir_Predefined_Ieee_1164_To_Bitvector; Set_Implicit_Definition (Decl, Predefined); - end; - elsif Is_Scalar_Function (Decl) then - declare - Predefined : Iir_Predefined_Functions; - begin - case Get_Identifier (Decl) is - when Name_Not => - Predefined := Iir_Predefined_Ieee_1164_Scalar_Not; - when Name_Op_Condition => - Predefined := - Iir_Predefined_Ieee_1164_Condition_Operator; - when others => - Predefined := Iir_Predefined_None; - end case; - Set_Implicit_Definition (Decl, Predefined); - end; - elsif Is_Vector_Vector_Function (Decl) then - declare - Predefined : Iir_Predefined_Functions; - begin - case Get_Identifier (Decl) is - when Name_And => - Predefined := Iir_Predefined_Ieee_1164_Vector_And; - when Name_Nand => - Predefined := Iir_Predefined_Ieee_1164_Vector_Nand; - when Name_Or => - Predefined := Iir_Predefined_Ieee_1164_Vector_Or; - when Name_Nor => - Predefined := Iir_Predefined_Ieee_1164_Vector_Nor; - when Name_Xor => - Predefined := Iir_Predefined_Ieee_1164_Vector_Xor; - when Name_Xnor => - Predefined := Iir_Predefined_Ieee_1164_Vector_Xnor; - when others => - Predefined := Iir_Predefined_None; - end case; - Set_Implicit_Definition (Decl, Predefined); - end; - elsif Is_Vector_Function (Decl) then - declare - Predefined : Iir_Predefined_Functions; - begin - case Get_Identifier (Decl) is - when Name_Not => - Predefined := Iir_Predefined_Ieee_1164_Vector_Not; - when Name_And => - Predefined := - Iir_Predefined_Ieee_1164_Vector_And_Reduce; - when Name_Or => - Predefined := - Iir_Predefined_Ieee_1164_Vector_Or_Reduce; - when others => - Predefined := Iir_Predefined_None; - end case; - Set_Implicit_Definition (Decl, Predefined); - end; - end if; + when others => + if Is_Scalar_Scalar_Function (Decl) then + case Get_Identifier (Decl) is + when Name_And => + Predefined := Iir_Predefined_Ieee_1164_Scalar_And; + when Name_Nand => + Predefined := Iir_Predefined_Ieee_1164_Scalar_Nand; + when Name_Or => + Predefined := Iir_Predefined_Ieee_1164_Scalar_Or; + when Name_Nor => + Predefined := Iir_Predefined_Ieee_1164_Scalar_Nor; + when Name_Xor => + Predefined := Iir_Predefined_Ieee_1164_Scalar_Xor; + when Name_Xnor => + Predefined := Iir_Predefined_Ieee_1164_Scalar_Xnor; + when others => + Predefined := Iir_Predefined_None; + end case; + Set_Implicit_Definition (Decl, Predefined); + elsif Is_Scalar_Function (Decl) then + case Get_Identifier (Decl) is + when Name_Not => + Predefined := Iir_Predefined_Ieee_1164_Scalar_Not; + when Name_Op_Condition => + Predefined := + Iir_Predefined_Ieee_1164_Condition_Operator; + when others => + Predefined := Iir_Predefined_None; + end case; + Set_Implicit_Definition (Decl, Predefined); + elsif Is_Vector_Vector_Function (Decl) then + case Get_Identifier (Decl) is + when Name_And => + Predefined := Iir_Predefined_Ieee_1164_Vector_And; + when Name_Nand => + Predefined := Iir_Predefined_Ieee_1164_Vector_Nand; + when Name_Or => + Predefined := Iir_Predefined_Ieee_1164_Vector_Or; + when Name_Nor => + Predefined := Iir_Predefined_Ieee_1164_Vector_Nor; + when Name_Xor => + Predefined := Iir_Predefined_Ieee_1164_Vector_Xor; + when Name_Xnor => + Predefined := Iir_Predefined_Ieee_1164_Vector_Xnor; + when others => + Predefined := Iir_Predefined_None; + end case; + Set_Implicit_Definition (Decl, Predefined); + elsif Is_Vector_Function (Decl) then + case Get_Identifier (Decl) is + when Name_Not => + Predefined := Iir_Predefined_Ieee_1164_Vector_Not; + when Name_And => + Predefined := + Iir_Predefined_Ieee_1164_Vector_And_Reduce; + when Name_Or => + Predefined := + Iir_Predefined_Ieee_1164_Vector_Or_Reduce; + when others => + Predefined := Iir_Predefined_None; + end case; + Set_Implicit_Definition (Decl, Predefined); + end if; + end case; end if; end loop; diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index 6d0bca05a..d5ed8a8fc 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -4910,6 +4910,8 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_1164_Vector_Xnor, Iir_Predefined_Ieee_1164_Vector_Not, + Iir_Predefined_Ieee_1164_To_Bitvector, + -- VHDL-2008 unary logic operators Iir_Predefined_Ieee_1164_Vector_And_Reduce, Iir_Predefined_Ieee_1164_Vector_Or_Reduce, |