synth: put direction into port desc

8 files changed, 30 insertions, 31 deletions

diff --git a/src/synth/netlists-builders.adb b/src/synth/netlists-builders.adb
index 56069f1b4..d0d4b20be 100644
--- a/src/synth/netlists-builders.adb
+++ b/src/synth/netlists-builders.adb
@@ -21,18 +21,22 @@ with Name_Table; use Name_Table;
 with Std_Names; use Std_Names;
 
 package body Netlists.Builders is
-   function Create_Input (Id : String; W : Width := 0) return Port_Desc is
+   function Create_Port (Id : String; Dir : Port_Kind; W : Width := 0)
+                        return Port_Desc is
    begin
       return (Name => New_Sname_Artificial (Get_Identifier (Id), No_Sname),
-              Is_Inout => False,
+              Dir => Dir,
               W => W);
+   end Create_Port;
+
+   function Create_Input (Id : String; W : Width := 0) return Port_Desc is
+   begin
+      return Create_Port (Id, Port_In, W);
    end Create_Input;
 
    function Create_Output (Id : String; W : Width := 0) return Port_Desc is
    begin
-      return (Name => New_Sname_Artificial (Get_Identifier (Id), No_Sname),
-              Is_Inout => False,
-              W => W);
+      return Create_Port (Id, Port_Out, W);
    end Create_Output;
 
    procedure Create_Dyadic_Module (Design : Module;
diff --git a/src/synth/netlists-disp_verilog.adb b/src/synth/netlists-disp_verilog.adb
index b6ceece5a..6bdb9186e 100644
--- a/src/synth/netlists-disp_verilog.adb
+++ b/src/synth/netlists-disp_verilog.adb
@@ -1240,7 +1240,6 @@ package body Netlists.Disp_Verilog is
    end Disp_Module_Statements;
 
    procedure Disp_Module_Port (Desc : Port_Desc;
-                               Dir : Port_Kind;
                                Attrs : Attribute;
                                First : in out Boolean)
    is
@@ -1268,7 +1267,7 @@ package body Netlists.Disp_Verilog is
          Put (" *) ");
       end if;
 
-      case Dir is
+      case Desc.Dir is
          when Port_In =>
             Put ("input  ");
          when Port_Out =>
@@ -1288,17 +1287,14 @@ package body Netlists.Disp_Verilog is
    begin
       First := True;
       for I in 1 .. Get_Nbr_Inputs (M) loop
+         Desc := Get_Input_Desc (M, I - 1);
          Attr := Get_Input_Port_First_Attribute (M, I - 1);
-         Disp_Module_Port (Get_Input_Desc (M, I - 1), Port_In, Attr, First);
+         Disp_Module_Port (Desc, Attr, First);
       end loop;
       for I in 1 .. Get_Nbr_Outputs (M) loop
          Desc := Get_Output_Desc (M, I - 1);
          Attr := Get_Output_Port_First_Attribute (M, I - 1);
-         if Desc.Is_Inout then
-            Disp_Module_Port (Desc, Port_Inout, Attr, First);
-         else
-            Disp_Module_Port (Desc, Port_Out, Attr, First);
-         end if;
+         Disp_Module_Port (Desc, Attr, First);
       end loop;
       if not First then
          Put (")");
diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb
index a9db40b11..580eec452 100644
--- a/src/synth/netlists-disp_vhdl.adb
+++ b/src/synth/netlists-disp_vhdl.adb
@@ -1521,8 +1521,7 @@ package body Netlists.Disp_Vhdl is
       New_Line;
    end Disp_Architecture;
 
-   procedure Disp_Entity_Port
-     (Desc : Port_Desc; Dir : Port_Kind; First : in out Boolean) is
+   procedure Disp_Entity_Port (Desc : Port_Desc; First : in out Boolean) is
    begin
       if First then
          Put_Line ("  port (");
@@ -1533,7 +1532,7 @@ package body Netlists.Disp_Vhdl is
       Put ("    ");
       Put_Name (Desc.Name);
       Put (" : ");
-      case Dir is
+      case Desc.Dir is
          when Port_In =>
             Put ("in");
          when Port_Out =>
@@ -1552,15 +1551,12 @@ package body Netlists.Disp_Vhdl is
    begin
       First := True;
       for I in 1 .. Get_Nbr_Inputs (M) loop
-         Disp_Entity_Port (Get_Input_Desc (M, I - 1), Port_In, First);
+         Desc := Get_Input_Desc (M, I - 1);
+         Disp_Entity_Port (Desc, First);
       end loop;
       for I in 1 .. Get_Nbr_Outputs (M) loop
          Desc := Get_Output_Desc (M, I - 1);
-         if Desc.Is_Inout then
-            Disp_Entity_Port (Desc, Port_Inout, First);
-         else
-            Disp_Entity_Port (Desc, Port_Out, First);
-         end if;
+         Disp_Entity_Port (Desc, First);
       end loop;
       if not First then
          Put_Line (");");
diff --git a/src/synth/netlists-utils.adb b/src/synth/netlists-utils.adb
index 45e498663..a73acca6b 100644
--- a/src/synth/netlists-utils.adb
+++ b/src/synth/netlists-utils.adb
@@ -99,7 +99,7 @@ package body Netlists.Utils is
 
    function Get_Inout_Flag (M : Module; I : Port_Idx) return Boolean is
    begin
-      return Get_Output_Desc (M, I).Is_Inout;
+      return Get_Output_Desc (M, I).Dir = Port_Inout;
    end Get_Inout_Flag;
 
    function Get_Input_Net (Inst : Instance; Idx : Port_Idx) return Net is
diff --git a/src/synth/netlists.adb b/src/synth/netlists.adb
index 3de0a69fb..c62604929 100644
--- a/src/synth/netlists.adb
+++ b/src/synth/netlists.adb
@@ -159,7 +159,7 @@ package body Netlists is
       Ports_Desc := Port_Desc_Table.Last + 1;
       for I in 1 .. Nbr_Inputs + Nbr_Outputs loop
          Port_Desc_Table.Append
-           ((Name => No_Sname, Is_Inout => False, W => 0));
+           ((Name => No_Sname, Dir => Port_In, W => 0));
       end loop;
 
       Modules_Table.Append
@@ -1575,7 +1575,7 @@ begin
    pragma Assert (Inputs_Table.Last = No_Input);
 
    Port_Desc_Table.Append ((Name => No_Sname,
-                            Is_Inout => False,
+                            Dir => Port_In,
                             W => 0));
    pragma Assert (Port_Desc_Table.Last = No_Port_Desc_Idx);
 
diff --git a/src/synth/netlists.ads b/src/synth/netlists.ads
index 365e1f1a2..661c2ae3d 100644
--- a/src/synth/netlists.ads
+++ b/src/synth/netlists.ads
@@ -152,7 +152,7 @@ package Netlists is
       --  Name of the port.
       Name : Sname;
 
-      Is_Inout : Boolean;
+      Dir : Port_Kind;
 
       --  Port width (number of bits).
       W : Width;
@@ -366,6 +366,9 @@ private
    type Sname is new Uns32 range 0 .. 2**30 - 1;
    No_Sname : constant Sname := 0;
 
+   --  Just to confirm.
+   for Port_Desc'Size use 64;
+
    --  We don't care about C compatible representation of Sname_Record.
    pragma Warnings (Off, "*convention*");
    type Sname_Record is record
diff --git a/src/synth/synth-disp_vhdl.adb b/src/synth/synth-disp_vhdl.adb
index 58f7989e7..8a5f4f863 100644
--- a/src/synth/synth-disp_vhdl.adb
+++ b/src/synth/synth-disp_vhdl.adb
@@ -63,7 +63,7 @@ package body Synth.Disp_Vhdl is
       end loop;
       for I in 1 .. Get_Nbr_Outputs (M) loop
          Desc := Get_Output_Desc (M, I - 1);
-         if not Desc.Is_Inout then
+         if Desc.Dir /= Port_Inout then
             --  inout ports are not prefixed, so they must not be declared
             --  as signals.
             Disp_Signal (Desc);
@@ -518,7 +518,7 @@ package body Synth.Disp_Vhdl is
          Pfx_Wrap := New_Sname_User (Name_Wrap, No_Sname);
          for P of Ports_Desc (Main) loop
             --  INOUT ports are handled specially.
-            if not P.Is_Inout then
+            if P.Dir /= Port_Inout then
                Pfx := Get_Sname_Prefix (P.Name);
                if Pfx = No_Sname then
                   --  Normal port, without a prefix.
diff --git a/src/synth/synth-vhdl_insts.adb b/src/synth/synth-vhdl_insts.adb
index 3c0ac47f8..2a44d7440 100644
--- a/src/synth/synth-vhdl_insts.adb
+++ b/src/synth/synth-vhdl_insts.adb
@@ -389,7 +389,7 @@ package body Synth.Vhdl_Insts is
            | Type_Unbounded_Array =>
             Idx := Idx + 1;
             Descs (Idx) := (Name => Port_Sname,
-                            Is_Inout => Pkind = Port_Inout,
+                            Dir => Pkind,
                             W => Get_Type_Width (Typ));
          when Type_Record
            | Type_Unbounded_Record =>
@@ -404,7 +404,7 @@ package body Synth.Vhdl_Insts is
                   Descs (Idx) :=
                     (Name => New_Sname_User
                        (Get_Encoded_Name_Id (El, Encoding), Port_Sname),
-                     Is_Inout => Pkind = Port_Inout,
+                     Dir => Pkind,
                      W => Get_Type_Width (Typ.Rec.E (I).Typ));
                end loop;
             end;
@@ -1383,7 +1383,7 @@ package body Synth.Vhdl_Insts is
          Init_Net := No_Net;
       end if;
 
-      if Desc.Is_Inout then
+      if Desc.Dir = Port_Inout then
          declare
             Io_Inst : Instance;
          begin