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authorTristan Gingold <tgingold@free.fr>2019-09-13 07:28:10 +0200
committerTristan Gingold <tgingold@free.fr>2019-09-13 07:28:10 +0200
commit2e61401a3d12ede4bb72bc6749d7f6ae905d6376 (patch)
treea26d4b8c1fc57882cb5ce9e1fb108b68735278c3
parent8f0227416720253cabacff0d0cb9ced2f660f981 (diff)
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synth: initialize subprogram variables.
-rw-r--r--src/synth/synth-decls.adb12
-rw-r--r--src/synth/synth-decls.ads6
-rw-r--r--src/synth/synth-expr.adb2
-rw-r--r--src/synth/synth-stmts.adb2
4 files changed, 14 insertions, 8 deletions
diff --git a/src/synth/synth-decls.adb b/src/synth/synth-decls.adb
index 20bd9323b..318493c8c 100644
--- a/src/synth/synth-decls.adb
+++ b/src/synth/synth-decls.adb
@@ -431,7 +431,8 @@ package body Synth.Decls is
end loop;
end Synth_Subprogram_Declaration;
- procedure Synth_Declaration (Syn_Inst : Synth_Instance_Acc; Decl : Node) is
+ procedure Synth_Declaration
+ (Syn_Inst : Synth_Instance_Acc; Decl : Node; Is_Subprg : Boolean) is
begin
case Get_Kind (Decl) is
when Iir_Kind_Variable_Declaration =>
@@ -449,6 +450,10 @@ package body Synth.Decls is
Init := null;
end if;
Create_Var_Wire (Syn_Inst, Decl, Init);
+ if Is_Subprg and then Init /= null then
+ Phi_Assign (Build_Context, Get_Value (Syn_Inst, Decl).W,
+ Get_Net (Init), 0);
+ end if;
end;
when Iir_Kind_Interface_Variable_Declaration =>
-- Ignore default value.
@@ -521,13 +526,14 @@ package body Synth.Decls is
end case;
end Synth_Declaration;
- procedure Synth_Declarations (Syn_Inst : Synth_Instance_Acc; Decls : Iir)
+ procedure Synth_Declarations
+ (Syn_Inst : Synth_Instance_Acc; Decls : Iir; Is_Subprg : Boolean := False)
is
Decl : Iir;
begin
Decl := Decls;
while Is_Valid (Decl) loop
- Synth_Declaration (Syn_Inst, Decl);
+ Synth_Declaration (Syn_Inst, Decl, Is_Subprg);
Decl := Get_Chain (Decl);
end loop;
diff --git a/src/synth/synth-decls.ads b/src/synth/synth-decls.ads
index aaae102c3..dda550ed9 100644
--- a/src/synth/synth-decls.ads
+++ b/src/synth/synth-decls.ads
@@ -33,7 +33,7 @@ package Synth.Decls is
procedure Synth_Declaration_Type
(Syn_Inst : Synth_Instance_Acc; Decl : Node);
- procedure Synth_Declaration (Syn_Inst : Synth_Instance_Acc; Decl : Node);
-
- procedure Synth_Declarations (Syn_Inst : Synth_Instance_Acc; Decls : Node);
+ procedure Synth_Declarations (Syn_Inst : Synth_Instance_Acc;
+ Decls : Iir;
+ Is_Subprg : Boolean := False);
end Synth.Decls;
diff --git a/src/synth/synth-expr.adb b/src/synth/synth-expr.adb
index 9ec249193..a4837e65b 100644
--- a/src/synth/synth-expr.adb
+++ b/src/synth/synth-expr.adb
@@ -95,7 +95,7 @@ package body Synth.Expr is
end From_Bit;
procedure To_Logic
- (Enum : Int64; Etype : Type_Acc; Val : out Uns32; Zx : out Uns32) is
+ (Enum : Int64; Etype : Type_Acc; Val : out Uns32; Zx : out Uns32) is
begin
if Etype = Logic_Type then
From_Std_Logic (Enum, Val, Zx);
diff --git a/src/synth/synth-stmts.adb b/src/synth/synth-stmts.adb
index 66ab2900b..6c616af69 100644
--- a/src/synth/synth-stmts.adb
+++ b/src/synth/synth-stmts.adb
@@ -1504,7 +1504,7 @@ package body Synth.Stmts is
Phi_Assign (Build_Context, C.W_Ret,
Build_Const_UB32 (Build_Context, 0, 1), 0);
- Decls.Synth_Declarations (C.Inst, Get_Declaration_Chain (Bod));
+ Decls.Synth_Declarations (C.Inst, Get_Declaration_Chain (Bod), True);
Synth_Sequential_Statements
(C, Get_Sequential_Statement_Chain (Bod));