synth: reuse signal name while creating memories. Fix #1838

5 files changed, 34 insertions, 20 deletions

diff --git a/src/synth/netlists-builders.adb b/src/synth/netlists-builders.adb
index 0de96d690..f396123e6 100644
--- a/src/synth/netlists-builders.adb
+++ b/src/synth/netlists-builders.adb
@@ -1226,27 +1226,28 @@ package body Netlists.Builders is
       return O;
    end Build_Addidx;
 
-   function Build_Memory (Ctxt : Context_Acc; W : Width) return Instance
+   function Build_Memory
+     (Ctxt : Context_Acc; Name : Sname; W : Width) return Instance
    is
       pragma Assert (W > 0);
       Inst : Instance;
       O : Net;
    begin
-      Inst := New_Internal_Instance (Ctxt, Ctxt.M_Memory);
+      Inst := New_Instance (Ctxt.Parent, Ctxt.M_Memory, Name);
       O := Get_Output (Inst, 0);
       Set_Width (O, W);
       return Inst;
    end Build_Memory;
 
-   function Build_Memory_Init (Ctxt : Context_Acc; W : Width; Init : Net)
-                              return Instance
+   function Build_Memory_Init
+     (Ctxt : Context_Acc; Name : Sname; W : Width; Init : Net) return Instance
    is
       pragma Assert (W > 0);
       pragma Assert (Get_Width (Init) = W);
       Inst : Instance;
       O : Net;
    begin
-      Inst := New_Internal_Instance (Ctxt, Ctxt.M_Memory_Init);
+      Inst := New_Instance (Ctxt.Parent, Ctxt.M_Memory_Init, Name);
       O := Get_Output (Inst, 0);
       Set_Width (O, W);
       Connect (Get_Input (Inst, 1), Init);
diff --git a/src/synth/netlists-builders.ads b/src/synth/netlists-builders.ads
index 04d675030..86a95851f 100644
--- a/src/synth/netlists-builders.ads
+++ b/src/synth/netlists-builders.ads
@@ -136,9 +136,11 @@ package Netlists.Builders is
       I : Net; Step : Uns32; Max : Uns32; W : Width) return Net;
    function Build_Addidx (Ctxt : Context_Acc; L, R : Net) return Net;
 
-   function Build_Memory (Ctxt : Context_Acc; W : Width) return Instance;
-   function Build_Memory_Init (Ctxt : Context_Acc; W : Width; Init : Net)
-                              return Instance;
+   function Build_Memory
+     (Ctxt : Context_Acc; Name : Sname; W : Width) return Instance;
+   function Build_Memory_Init
+     (Ctxt : Context_Acc; Name : Sname; W : Width; Init : Net) return Instance;
+
    function Build_Mem_Rd
      (Ctxt : Context_Acc; Pport : Net; Addr : Net; Data_W : Width)
      return Instance;
diff --git a/src/synth/netlists-disp_verilog.adb b/src/synth/netlists-disp_verilog.adb
index c0c6f0c0a..26c511480 100644
--- a/src/synth/netlists-disp_verilog.adb
+++ b/src/synth/netlists-disp_verilog.adb
@@ -676,7 +676,7 @@ package body Netlists.Disp_Verilog is
       --  Declare the memory.
       Put ("  reg ");
       Put_Type (Data_W);
-      Disp_Net_Name (Ports);
+      Put_Name (Get_Instance_Name (Mem));
       Put_Type (Depth);
       Put_Line("; // memory");
 
@@ -704,18 +704,18 @@ package body Netlists.Disp_Verilog is
                  ("  always @(\ei2)" & NL &
                   "    if (\i3)" & NL, Port_Inst);
                Disp_Template
-                 ("      \o0", Mem);
+                 ("      \l0", Mem);
                Disp_Template ("[\i1] <= \i4;" & NL, Port_Inst);
             when Id_Mem_Rd =>
                Disp_Template ("  assign \o1 = ", Port_Inst);
-               Disp_Template ("\o0", Mem);
+               Disp_Template ("\l0", Mem);
                Disp_Template ("[\i1];" & NL, Port_Inst);
             when Id_Mem_Rd_Sync =>
                Disp_Template
                  ("  always @(\ei2)" & NL &
                   "    if (\i3)" & NL &
                   "      \o1 <= ", Port_Inst);
-               Disp_Template ("\o0", Mem);
+               Disp_Template ("\l0", Mem);
                Disp_Template ("[\i1];" & NL, Port_Inst);
             when Id_Memory
               | Id_Memory_Init =>
diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb
index ce25ca15b..79e86bc36 100644
--- a/src/synth/netlists-disp_vhdl.adb
+++ b/src/synth/netlists-disp_vhdl.adb
@@ -750,7 +750,7 @@ package body Netlists.Disp_Vhdl is
       Depth := Get_Width (Ports) / Data_W;
 
       --  Declare the memory.
-      Disp_Template ("    type \o0_type is array (0 to \n0)" & NL,
+      Disp_Template ("    type \l0_type is array (0 to \n0)" & NL,
                      Mem, (0 => Depth - 1));
       if Data_W = 1 then
          Disp_Template ("      of std_logic;" & NL, Mem);
@@ -758,7 +758,7 @@ package body Netlists.Disp_Vhdl is
          Disp_Template ("      of std_logic_vector (\n0 downto 0);" & NL,
                         Mem, (0 => Data_W - 1));
       end if;
-      Disp_Template ("    variable \o0 : \o0_type", Mem);
+      Disp_Template ("    variable \l0 : \l0_type", Mem);
       if Get_Id (Mem) = Id_Memory_Init then
          declare
             Val : Net;
@@ -785,19 +785,19 @@ package body Netlists.Disp_Vhdl is
                Disp_Template
                  ("    if \ei2 and (\fi3 = '1') then" & NL,
                   Port_Inst);
-               Disp_Template ("      \o0 (", Mem);
+               Disp_Template ("      \l0 (", Mem);
                Disp_Template ("to_integer (\ui1)) := \i4;" & NL, Port_Inst);
                Put_Line ("    end if;");
             when Id_Mem_Rd =>
                Disp_Template ("    \o1 <= ", Port_Inst);
-               Disp_Template ("\o0", Mem);
+               Disp_Template ("\l0", Mem);
                Disp_Template ("(to_integer (\ui1));" & NL, Port_Inst);
             when Id_Mem_Rd_Sync =>
                Disp_Template
                  ("    if \ei2 and (\fi3 = '1') then" & NL,
                   Port_Inst);
                Disp_Template ("      \o1 <= ", Port_Inst);
-               Disp_Template ("\o0", Mem);
+               Disp_Template ("\l0", Mem);
                Disp_Template ("(to_integer (\ui1));" & NL, Port_Inst);
                Put_Line ("    end if;");
             when Id_Memory
diff --git a/src/synth/netlists-memories.adb b/src/synth/netlists-memories.adb
index 0b9853b83..0b8d62f84 100644
--- a/src/synth/netlists-memories.adb
+++ b/src/synth/netlists-memories.adb
@@ -1141,9 +1141,10 @@ package body Netlists.Memories is
      (Ctxt : Context_Acc; Orig : Instance; Step : Width)
    is
       Orig_Net : constant Net := Get_Output (Orig, 0);
+      Name : constant Sname := New_Internal_Name (Ctxt);
       Inst : Instance;
    begin
-      Inst := Build_Memory_Init (Ctxt, Get_Width (Orig_Net), Orig_Net);
+      Inst := Build_Memory_Init (Ctxt, Name, Get_Width (Orig_Net), Orig_Net);
 
       Replace_Read_Ports (Ctxt, Orig, Inst, Step);
    end Replace_ROM_Memory;
@@ -2153,6 +2154,8 @@ package body Netlists.Memories is
       --  Size of RAM (in bits).
       Mem_Sz : constant Uns32 := Get_Width (Get_Output (Sig, 0));
 
+      Sig_Name : constant Sname := Get_Instance_Name (Sig);
+
       --  Width of the RAM, computed from the step of memidx.
       Mem_W : Width;
 
@@ -2162,6 +2165,7 @@ package body Netlists.Memories is
 
       Nbr_Ports : Int32;
       Inst : Instance;
+      Name : Sname;
 
       --  Table of offsets.
       --  The same RAM can be partially read or written: not all the bits of
@@ -2257,6 +2261,13 @@ package body Netlists.Memories is
 
       --  4. Create Memory/Memory_Init from signal/isignal.
       for I in 1 .. Nbr_Offs - 1 loop
+         --  Reuse signal name for the memory name.
+         if Nbr_Offs = 2 then
+            Name := Sig_Name;
+         else
+            Name := New_Sname_Version (Uns32 (I), Sig_Name);
+         end if;
+
          declare
             Data_Wd : constant Width := Offs (I + 1) - Offs (I);
             Mem_Wd : constant Width := Data_Wd * Mem_Depth;
@@ -2264,12 +2275,12 @@ package body Netlists.Memories is
             case Get_Id (Sig) is
                when Id_Isignal =>
                   Heads (I) := Build_Memory_Init
-                    (Ctxt, Mem_Wd,
+                    (Ctxt, Name, Mem_Wd,
                      Extract_Sub_Constant
                        (Ctxt, Get_Input_Instance (Sig, 1),
                         Mem_W, Offs (I), Data_Wd, Mem_Depth));
                when Id_Signal =>
-                  Heads (I) := Build_Memory (Ctxt, Mem_Wd);
+                  Heads (I) := Build_Memory (Ctxt, Name, Mem_Wd);
                when others =>
                   raise Internal_Error;
             end case;