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| author | Tristan Gingold <tgingold@free.fr> | 2020-08-06 19:53:39 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-08-06 19:53:39 +0200 |
| commit | 3055b10198071f23e3b6eb2b7c2a1587c9cb4ec8 (patch) | |
| tree | dbe3fb32f0443d95b9a90f233cc28c6798c12e87 | |
| parent | 98bf726697e42c26c271467380779d905c6a8008 (diff) | |
| download | ghdl-3055b10198071f23e3b6eb2b7c2a1587c9cb4ec8.tar.gz ghdl-3055b10198071f23e3b6eb2b7c2a1587c9cb4ec8.tar.bz2 ghdl-3055b10198071f23e3b6eb2b7c2a1587c9cb4ec8.zip | |
synth-disp_vhdl: minor output indentation fix.
| -rw-r--r-- | src/synth/synth-disp_vhdl.adb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/synth/synth-disp_vhdl.adb b/src/synth/synth-disp_vhdl.adb index 2e895a08c..e9e99fa6f 100644 --- a/src/synth/synth-disp_vhdl.adb +++ b/src/synth/synth-disp_vhdl.adb @@ -318,7 +318,7 @@ package body Synth.Disp_Vhdl is -- netlist. Put ("(0 => to_bit ("); else - Put (" to_bitvector ("); + Put ("to_bitvector ("); end if; Disp_Out_Rhs (Mname, Off, W, Full); if W = 1 then |