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authorTristan Gingold <tgingold@free.fr>2019-06-30 14:03:13 +0200
committerTristan Gingold <tgingold@free.fr>2019-06-30 14:03:13 +0200
commit33884b2801f3b9cd52a0e6c20ee0d1079982c43d (patch)
tree2d6736f7232ac0f91a8c8fd5810ed2ec28b42bab
parent181165f90d7ab05cff1c2bc5894d0143f03d3634 (diff)
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synth: handle various enum ranges for case stmts.
-rw-r--r--src/synth/synth-stmts.adb28
1 files changed, 24 insertions, 4 deletions
diff --git a/src/synth/synth-stmts.adb b/src/synth/synth-stmts.adb
index 7ac5053e2..f2d9f48e5 100644
--- a/src/synth/synth-stmts.adb
+++ b/src/synth/synth-stmts.adb
@@ -503,6 +503,7 @@ package body Synth.Stmts is
S_Group : constant Uns64 := Els (Iels).Sel and Mask;
S_El : Uns64;
El_Idx : Natural;
+ Rsel : Net;
begin
G := (others => Default);
for K in 0 .. 3 loop
@@ -514,10 +515,29 @@ package body Synth.Stmts is
G (El_Idx) := Els (Iels).Val;
Iels := Iels + 1;
end loop;
- Els (Oels) :=
- (Sel => S_Group,
- Val => Build_Mux4 (Build_Context,
- Sub_Sel, G (0), G (1), G (2), G (3)));
+ if G (3) /= No_Net then
+ Rsel := Build_Mux4 (Build_Context,
+ Sub_Sel, G (0), G (1), G (2), G (3));
+ elsif G (2) /= No_Net then
+ Rsel := Build_Mux2
+ (Build_Context,
+ Build_Extract_Bit (Build_Context,
+ Sel, Width (2 * (I - 1)) + 1),
+ Build_Mux2 (Build_Context,
+ Build_Extract_Bit (Build_Context,
+ Sel, Width (2 * (I - 1))),
+ G (0), G (1)),
+ G (2));
+ elsif G (1) /= No_Net then
+ Rsel := Build_Mux2
+ (Build_Context,
+ Build_Extract_Bit (Build_Context,
+ Sel, Width (2 * (I - 1))),
+ G (0), G (1));
+ else
+ Rsel := G (0);
+ end if;
+ Els (Oels) := (Sel => S_Group, Val => Rsel);
Oels := Oels + 1;
end;
end loop;