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| author | Tristan Gingold <tgingold@free.fr> | 2021-04-21 19:29:09 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2021-04-21 19:32:51 +0200 |
| commit | 37f4aea448ae353c9ffd4254ffcc8102d6ef9f0f (patch) | |
| tree | 6715504e886ec5b46ff4a6d7b8ad115f7177313b | |
| parent | 2d3f560ae6eb022283bd29a1157bfd60af53fcbb (diff) | |
| download | ghdl-37f4aea448ae353c9ffd4254ffcc8102d6ef9f0f.tar.gz ghdl-37f4aea448ae353c9ffd4254ffcc8102d6ef9f0f.tar.bz2 ghdl-37f4aea448ae353c9ffd4254ffcc8102d6ef9f0f.zip | |
synth-vhdl_oper.adb: handle resize sgn/sgn. Fix #1731
With an hint from T.Meissner
| -rw-r--r-- | src/synth/synth-vhdl_oper.adb | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/synth/synth-vhdl_oper.adb b/src/synth/synth-vhdl_oper.adb index 0a3075b94..f741d7fc7 100644 --- a/src/synth/synth-vhdl_oper.adb +++ b/src/synth/synth-vhdl_oper.adb @@ -1961,6 +1961,7 @@ package body Synth.Vhdl_Oper is Create_Vec_Type_By_Length (W, Logic_Type)); end; when Iir_Predefined_Ieee_Numeric_Std_Resize_Sgn_Nat + | Iir_Predefined_Ieee_Numeric_Std_Resize_Sgn_Sgn | Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Vector_Sgn | Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Sgn | Iir_Predefined_Ieee_Std_Logic_Arith_Sxt => |