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author | Tristan Gingold <tgingold@free.fr> | 2019-11-12 20:27:22 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-11-12 20:36:04 +0100 |
commit | 3aed7e6e47610750f50cce9bdc547f975e01e656 (patch) | |
tree | dd73f646b6e2bbff0289740eab5aaca37dcba8e7 | |
parent | 72d9a475e19ab200b87975750dced5ab47994aac (diff) | |
download | ghdl-3aed7e6e47610750f50cce9bdc547f975e01e656.tar.gz ghdl-3aed7e6e47610750f50cce9bdc547f975e01e656.tar.bz2 ghdl-3aed7e6e47610750f50cce9bdc547f975e01e656.zip |
testsuite/synth: add a test for static values.
-rw-r--r-- | testsuite/synth/const01/const01.vhdl | 29 | ||||
-rw-r--r-- | testsuite/synth/const01/tb_const01.vhdl | 20 | ||||
-rwxr-xr-x | testsuite/synth/const01/testsuite.sh | 16 |
3 files changed, 65 insertions, 0 deletions
diff --git a/testsuite/synth/const01/const01.vhdl b/testsuite/synth/const01/const01.vhdl new file mode 100644 index 000000000..5e908d89b --- /dev/null +++ b/testsuite/synth/const01/const01.vhdl @@ -0,0 +1,29 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity const01 is + port (o : out std_logic_vector(0 to 31)); +end const01; + +architecture behav of const01 is + type slv_array is array (natural range <>) of std_logic_vector(7 downto 0); + + function conv (v : std_logic_vector) return slv_array is + variable r : slv_array(0 to v'length / 8 - 1); + begin + for i in 0 to r'length-1 loop + r (i) := v(v'length - (i*8) - 1 downto v'length - (i*8) - 8); + end loop; + return r; + end conv; + + constant init : std_logic_vector (31 downto 0) := x"01020304"; + constant res : slv_array (0 to 3) := conv (init); +begin + o (0 to 7) <= res (0); + o (8 to 15) <= res (1); + o (16 to 23) <= res (2); + o (24 to 31) <= res (3); +end behav; + + diff --git a/testsuite/synth/const01/tb_const01.vhdl b/testsuite/synth/const01/tb_const01.vhdl new file mode 100644 index 000000000..b5fad5833 --- /dev/null +++ b/testsuite/synth/const01/tb_const01.vhdl @@ -0,0 +1,20 @@ +entity tb_const01 is +end tb_const01; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_const01 is + signal res : std_logic_vector(31 downto 0); +begin + dut: entity work.const01 + port map (res); + + process + begin + wait for 1 ns; + assert res = x"01020304" severity failure; + + wait; + end process; +end behav; diff --git a/testsuite/synth/const01/testsuite.sh b/testsuite/synth/const01/testsuite.sh new file mode 100755 index 000000000..1a49d8a5d --- /dev/null +++ b/testsuite/synth/const01/testsuite.sh @@ -0,0 +1,16 @@ +#! /bin/sh + +. ../../testenv.sh + +for t in const01; do + analyze $t.vhdl tb_$t.vhdl + elab_simulate tb_$t + clean + + synth $t.vhdl -e $t > syn_$t.vhdl + analyze syn_$t.vhdl tb_$t.vhdl + elab_simulate tb_$t --ieee-asserts=disable-at-0 + clean +done + +echo "Test successful" |