synth: add Get_Build (WIP).

4 files changed, 20 insertions, 8 deletions

diff --git a/src/synth/synth-context.adb b/src/synth/synth-context.adb
index ecc36fa75..b6c5916b5 100644
--- a/src/synth/synth-context.adb
+++ b/src/synth/synth-context.adb
@@ -49,6 +49,7 @@ package body Synth.Context is
    begin
       Top_Module :=
         New_Design (New_Sname_Artificial (Get_Identifier ("top")));
+      pragma Assert (Build_Context = null);
       Build_Context := Build_Builders (Top_Module);
 
       Base := new Base_Instance_Type'(Builder => Build_Context,
@@ -129,6 +130,12 @@ package body Synth.Context is
       return Inst.Name;
    end Get_Sname;
 
+   function Get_Build (Inst : Synth_Instance_Acc)
+                      return Netlists.Builders.Context_Acc is
+   begin
+      return Inst.Base.Builder;
+   end Get_Build;
+
    function Create_Value_Instance (Inst : Synth_Instance_Acc)
                                   return Value_Acc is
    begin
diff --git a/src/synth/synth-context.ads b/src/synth/synth-context.ads
index 2b7aaeeab..296c89a78 100644
--- a/src/synth/synth-context.ads
+++ b/src/synth/synth-context.ads
@@ -51,6 +51,10 @@ package Synth.Context is
    function Get_Sname (Inst : Synth_Instance_Acc) return Sname;
    pragma Inline (Get_Sname);
 
+   function Get_Build (Inst : Synth_Instance_Acc)
+                      return Netlists.Builders.Context_Acc;
+   pragma Inline (Get_Build);
+
    function Get_Top_Module (Inst : Synth_Instance_Acc) return Module;
 
    procedure Set_Instance_Module (Inst : Synth_Instance_Acc; M : Module);
diff --git a/src/synth/synth-decls.adb b/src/synth/synth-decls.adb
index f2f7b5d5e..122e8ca99 100644
--- a/src/synth/synth-decls.adb
+++ b/src/synth/synth-decls.adb
@@ -54,9 +54,9 @@ package body Synth.Decls is
             if Init /= null then
                Ival := Get_Net (Init);
                pragma Assert (Get_Width (Ival) = W);
-               Value := Build_Isignal (Build_Context, Name, Ival);
+               Value := Build_Isignal (Get_Build (Syn_Inst), Name, Ival);
             else
-               Value := Build_Signal (Build_Context, Name, W);
+               Value := Build_Signal (Get_Build (Syn_Inst), Name, W);
             end if;
             Set_Location (Value, Decl);
             Set_Wire_Gate (Val.W, Value);
@@ -463,8 +463,8 @@ package body Synth.Decls is
                end if;
                Create_Var_Wire (Syn_Inst, Decl, Init);
                if Is_Subprg and then Init /= null then
-                  Phi_Assign (Build_Context, Get_Value (Syn_Inst, Decl).W,
-                              Get_Net (Init), 0);
+                  Phi_Assign (Get_Build (Syn_Inst),
+                              Get_Value (Syn_Inst, Decl).W, Get_Net (Init), 0);
                end if;
             end;
          when Iir_Kind_Interface_Variable_Declaration =>
diff --git a/src/synth/synth-insts.adb b/src/synth/synth-insts.adb
index 2eacb96e3..793717764 100644
--- a/src/synth/synth-insts.adb
+++ b/src/synth/synth-insts.adb
@@ -307,7 +307,7 @@ package body Synth.Insts is
               | Port_Inout =>
                if Actual /= Null_Iir then
                   Port := Get_Output (Inst, Nbr_Outputs);
-                  Port := Builders.Build_Port (Build_Context, Port);
+                  Port := Builders.Build_Port (Get_Build (Syn_Inst), Port);
                   O := Create_Value_Net
                     (Port, Get_Value_Type (Inst_Obj.Syn_Inst,
                                            Get_Type (Inter)));
@@ -583,7 +583,7 @@ package body Synth.Insts is
                when Port_Out
                  | Port_Inout =>
                   Port := Get_Output (Inst, Nbr_Outputs);
-                  Port := Builders.Build_Port (Build_Context, Port);
+                  Port := Builders.Build_Port (Get_Build (Syn_Inst), Port);
                   O := Create_Value_Net
                     (Port, Get_Value_Type (Syn_Inst, Get_Type (Inter)));
                   Synth_Assignment (Syn_Inst, Actual, O, Assoc);
@@ -775,7 +775,8 @@ package body Synth.Insts is
       end if;
 
       Self_Inst := Create_Self_Instance (Get_Instance_Module (Syn_Inst));
-      Builders.Set_Parent (Build_Context, Get_Instance_Module (Syn_Inst));
+      Builders.Set_Parent (Get_Build (Syn_Inst),
+                           Get_Instance_Module (Syn_Inst));
 
       --  Create wires for inputs and outputs.
       Inter := Get_Port_Chain (Entity);
@@ -810,7 +811,7 @@ package body Synth.Insts is
       Synth_Verification_Units (Syn_Inst, Entity);
       Synth_Verification_Units (Syn_Inst, Arch);
 
-      Finalize_Assignments (Build_Context);
+      Finalize_Assignments (Get_Build (Syn_Inst));
 
       --  Remove unused gates.  This is not only an optimization but also
       --  a correctness point: there might be some unsynthesizable gates, like