testsuite/gna: add a test for #2336

6 files changed, 456 insertions, 0 deletions

diff --git a/testsuite/gna/issue2336/crash.vhdl b/testsuite/gna/issue2336/crash.vhdl
new file mode 100644
index 000000000..d172cc3db
--- /dev/null
+++ b/testsuite/gna/issue2336/crash.vhdl
@@ -0,0 +1,15 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity repro is
+  port (a, b, clk : std_logic);
+end;
+
+architecture behav of repro is
+begin
+  default clock is rising_edge(clk);
+
+   -- This assertion should hold, but doesn't (GHDL BUG)
+  NEXT_0_a : assert always (a -> next_event_e('1')[1 to 1] (b))
+    report "NEXT_0_a failed";
+end behav;
diff --git a/testsuite/gna/issue2336/repro.vhdl b/testsuite/gna/issue2336/repro.vhdl
new file mode 100644
index 000000000..b0f6a6c90
--- /dev/null
+++ b/testsuite/gna/issue2336/repro.vhdl
@@ -0,0 +1,17 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity repro is
+  port (a, b, clk : std_logic);
+end;
+
+architecture behav of repro is
+begin
+  default clock is rising_edge(clk);
+
+   -- This assertion should hold, but doesn't (GHDL BUG)
+--  NEXT_0_a : assert always (a -> next_event_e(true)[2 to 2] (b));
+--    NEXT_1_a : assert always (a -> next_e[2 to 4] (b));
+--    NEXT_2_a : assert always (a -> {true[->2 to 3] : b});
+  NEXT_3_a : assert always (a -> {true[->2 to 3] ; b});
+end behav;
diff --git a/testsuite/gna/issue2336/test_issue.vhdl b/testsuite/gna/issue2336/test_issue.vhdl
new file mode 100644
index 000000000..be7711f5d
--- /dev/null
+++ b/testsuite/gna/issue2336/test_issue.vhdl
@@ -0,0 +1,136 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+
+entity sequencer is
+  generic (
+    seq : string
+  );
+  port (
+    clk  : in  std_logic;
+    data : out std_logic
+  );
+end entity sequencer;
+
+architecture rtl of sequencer is
+
+  signal index : natural := seq'low;
+
+  function to_bit (a : in character) return std_logic is
+    variable ret : std_logic;
+  begin
+    case a is
+      when '0' | '_' => ret := '0';
+      when '1' | '-' => ret := '1';
+      when others    => ret := 'X';
+    end case;
+    return ret;
+  end function to_bit;
+
+begin
+
+  process (clk) is
+  begin
+    if rising_edge(clk) then
+      if (index < seq'high) then
+        index <= index + 1;
+      end if;
+    end if;
+  end process;
+
+  data <= to_bit(seq(index));
+
+end architecture rtl;
+
+
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.numeric_std.all;
+
+entity issue is
+  port (
+    clk : in std_logic
+  );
+end entity issue;
+
+architecture psl of issue is
+
+  signal a, b, c, d, e, f : std_logic;
+
+begin
+
+
+  --                                          012345678901
+  SEQ_A : entity work.sequencer generic map ("__-_________") port map (clk, a);
+
+  -- Next 3 sequences should hold with next[3:5]
+  --                                          012345678901
+  SEQ_B : entity work.sequencer generic map ("_____-______") port map (clk, b);
+  SEQ_C : entity work.sequencer generic map ("______-_____") port map (clk, c);
+  SEQ_D : entity work.sequencer generic map ("_______-____") port map (clk, d);
+
+  -- Next two sequences should not hold with next[3:5]
+  --                                          012345678901
+  SEQ_E : entity work.sequencer generic map ("____-_______") port map (clk, e);
+  SEQ_F : entity work.sequencer generic map ("________-___") port map (clk, f);
+
+
+  -- All is sensitive to rising edge of clk
+  default clock is rising_edge(clk);
+
+   -- This assertion should hold, but doesn't (GHDL BUG)
+  NEXT_0_a : assert always (a -> next_e[3 to 5] (b))
+    report "NEXT_0_a failed";
+
+  -- This assertion should hold, but doesn't (GHDL BUG)
+  NEXT_1_a : assert always (a -> next_e[3 to 5] (c))
+    report "NEXT_1_a failed";
+
+  -- This assertion holds (CORRECT)
+  NEXT_2_a : assert always (a -> next_e[3 to 5] (d))
+    report "NEXT_2_a failed";
+
+  -- This assertion doesn't hold (CORRECT)
+  NEXT_3_a : assert always (a -> next_e[3 to 5] (e))
+    report "NEXT_3_a failed";
+
+  -- This assertion doesn't hold (CORRECT)
+  NEXT_4_a : assert always (a -> next_e[3 to 5] (f))
+    report "NEXT_4_a failed";
+
+end architecture psl;
+
+library ieee;
+  use ieee.std_logic_1164.all;
+
+use std.env.all;
+
+
+entity test_issue is
+end entity test_issue;
+
+
+architecture sim of test_issue is
+
+  signal clk   : std_logic := '1';
+
+begin
+
+
+  clk <= not clk after 500 ps;
+
+  DUT : entity work.issue(psl) port map (clk);
+
+  -- stop simulation after 30 cycles
+  process
+    variable index : natural := 10;
+  begin
+    loop
+      wait until rising_edge(clk);
+      index := index - 1;
+      exit when index = 0;
+    end loop;
+    stop(0);
+  end process;
+
+
+end architecture sim;
diff --git a/testsuite/gna/issue2336/test_issue_err1.vhdl b/testsuite/gna/issue2336/test_issue_err1.vhdl
new file mode 100644
index 000000000..b157f8ddf
--- /dev/null
+++ b/testsuite/gna/issue2336/test_issue_err1.vhdl
@@ -0,0 +1,136 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+
+entity sequencer is
+  generic (
+    seq : string
+  );
+  port (
+    clk  : in  std_logic;
+    data : out std_logic
+  );
+end entity sequencer;
+
+architecture rtl of sequencer is
+
+  signal index : natural := seq'low;
+
+  function to_bit (a : in character) return std_logic is
+    variable ret : std_logic;
+  begin
+    case a is
+      when '0' | '_' => ret := '0';
+      when '1' | '-' => ret := '1';
+      when others    => ret := 'X';
+    end case;
+    return ret;
+  end function to_bit;
+
+begin
+
+  process (clk) is
+  begin
+    if rising_edge(clk) then
+      if (index < seq'high) then
+        index <= index + 1;
+      end if;
+    end if;
+  end process;
+
+  data <= to_bit(seq(index));
+
+end architecture rtl;
+
+
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.numeric_std.all;
+
+entity issue_err1 is
+  port (
+    clk : in std_logic
+  );
+end entity;
+
+architecture psl of issue_err1 is
+
+  signal a, b, c, d, e, f : std_logic;
+
+begin
+
+
+  --                                          012345678901
+  SEQ_A : entity work.sequencer generic map ("__-_________") port map (clk, a);
+
+  -- Next 3 sequences should hold with next[3:5]
+  --                                          012345678901
+  SEQ_B : entity work.sequencer generic map ("_____-______") port map (clk, b);
+  SEQ_C : entity work.sequencer generic map ("______-_____") port map (clk, c);
+  SEQ_D : entity work.sequencer generic map ("_______-____") port map (clk, d);
+
+  -- Next two sequences should not hold with next[3:5]
+  --                                          012345678901
+  SEQ_E : entity work.sequencer generic map ("____-_______") port map (clk, e);
+  SEQ_F : entity work.sequencer generic map ("________-___") port map (clk, f);
+
+
+  -- All is sensitive to rising edge of clk
+  default clock is rising_edge(clk);
+
+   -- This assertion should hold, but doesn't (GHDL BUG)
+  NEXT_0_a : assert always (a -> next_e[3 to 5] (b))
+    report "NEXT_0_a failed";
+
+  -- This assertion should hold, but doesn't (GHDL BUG)
+  NEXT_1_a : assert always (a -> next_e[3 to 5] (c))
+    report "NEXT_1_a failed";
+
+  -- This assertion holds (CORRECT)
+  NEXT_2_a : assert always (a -> next_e[3 to 5] (d))
+    report "NEXT_2_a failed";
+
+  -- This assertion doesn't hold (CORRECT)
+  NEXT_3_a : assert always (a -> next_e[3 to 5] (e))
+    report "NEXT_3_a failed";
+
+  -- This assertion doesn't hold (CORRECT)
+--  NEXT_4_a : assert always (a -> next_e[3 to 5] (f))
+--    report "NEXT_4_a failed";
+
+end architecture psl;
+
+library ieee;
+  use ieee.std_logic_1164.all;
+
+use std.env.all;
+
+
+entity test_issue_err1 is
+end entity test_issue_err1;
+
+
+architecture sim of test_issue_err1 is
+
+  signal clk   : std_logic := '1';
+
+begin
+
+
+  clk <= not clk after 500 ps;
+
+  DUT : entity work.issue_err1(psl) port map (clk);
+
+  -- stop simulation after 30 cycles
+  process
+    variable index : natural := 10;
+  begin
+    loop
+      wait until rising_edge(clk);
+      index := index - 1;
+      exit when index = 0;
+    end loop;
+    stop(0);
+  end process;
+
+
+end architecture sim;
diff --git a/testsuite/gna/issue2336/test_issue_ok.vhdl b/testsuite/gna/issue2336/test_issue_ok.vhdl
new file mode 100644
index 000000000..df0b2a731
--- /dev/null
+++ b/testsuite/gna/issue2336/test_issue_ok.vhdl
@@ -0,0 +1,136 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+
+entity sequencer is
+  generic (
+    seq : string
+  );
+  port (
+    clk  : in  std_logic;
+    data : out std_logic
+  );
+end entity sequencer;
+
+architecture rtl of sequencer is
+
+  signal index : natural := seq'low;
+
+  function to_bit (a : in character) return std_logic is
+    variable ret : std_logic;
+  begin
+    case a is
+      when '0' | '_' => ret := '0';
+      when '1' | '-' => ret := '1';
+      when others    => ret := 'X';
+    end case;
+    return ret;
+  end function to_bit;
+
+begin
+
+  process (clk) is
+  begin
+    if rising_edge(clk) then
+      if (index < seq'high) then
+        index <= index + 1;
+      end if;
+    end if;
+  end process;
+
+  data <= to_bit(seq(index));
+
+end architecture rtl;
+
+
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.numeric_std.all;
+
+entity issue_ok is
+  port (
+    clk : in std_logic
+  );
+end entity;
+
+architecture psl of issue_ok is
+
+  signal a, b, c, d, e, f : std_logic;
+
+begin
+
+
+  --                                          012345678901
+  SEQ_A : entity work.sequencer generic map ("__-_________") port map (clk, a);
+
+  -- Next 3 sequences should hold with next[3:5]
+  --                                          012345678901
+  SEQ_B : entity work.sequencer generic map ("_____-______") port map (clk, b);
+  SEQ_C : entity work.sequencer generic map ("______-_____") port map (clk, c);
+  SEQ_D : entity work.sequencer generic map ("_______-____") port map (clk, d);
+
+  -- Next two sequences should not hold with next[3:5]
+  --                                          012345678901
+  SEQ_E : entity work.sequencer generic map ("____-_______") port map (clk, e);
+  SEQ_F : entity work.sequencer generic map ("________-___") port map (clk, f);
+
+
+  -- All is sensitive to rising edge of clk
+  default clock is rising_edge(clk);
+
+   -- This assertion should hold, but doesn't (GHDL BUG)
+  NEXT_0_a : assert always (a -> next_e[3 to 5] (b))
+    report "NEXT_0_a failed";
+
+  -- This assertion should hold, but doesn't (GHDL BUG)
+  NEXT_1_a : assert always (a -> next_e[3 to 5] (c))
+    report "NEXT_1_a failed";
+
+  -- This assertion holds (CORRECT)
+  NEXT_2_a : assert always (a -> next_e[3 to 5] (d))
+    report "NEXT_2_a failed";
+
+  -- This assertion doesn't hold (CORRECT)
+--  NEXT_3_a : assert always (a -> next_e[3 to 5] (e))
+--    report "NEXT_3_a failed";
+
+  -- This assertion doesn't hold (CORRECT)
+--  NEXT_4_a : assert always (a -> next_e[3 to 5] (f))
+--    report "NEXT_4_a failed";
+
+end architecture psl;
+
+library ieee;
+  use ieee.std_logic_1164.all;
+
+use std.env.all;
+
+
+entity test_issue_ok is
+end entity test_issue_ok;
+
+
+architecture sim of test_issue_ok is
+
+  signal clk   : std_logic := '1';
+
+begin
+
+
+  clk <= not clk after 500 ps;
+
+  DUT : entity work.issue_ok(psl) port map (clk);
+
+  -- stop simulation after 30 cycles
+  process
+    variable index : natural := 10;
+  begin
+    loop
+      wait until rising_edge(clk);
+      index := index - 1;
+      exit when index = 0;
+    end loop;
+    stop(0);
+  end process;
+
+
+end architecture sim;
diff --git a/testsuite/gna/issue2336/testsuite.sh b/testsuite/gna/issue2336/testsuite.sh
new file mode 100755
index 000000000..7edc76ef1
--- /dev/null
+++ b/testsuite/gna/issue2336/testsuite.sh
@@ -0,0 +1,16 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+analyze test_issue_ok.vhdl
+elab_simulate test_issue_ok --assert-level=error
+
+clean
+
+analyze test_issue_err1.vhdl
+elab_simulate_failure test_issue_err1 --assert-level=error
+
+clean
+
+echo "Test successful"