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| author | Tristan Gingold <tgingold@free.fr> | 2019-10-01 07:50:12 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-10-01 07:50:12 +0200 |
| commit | 410178f09ab8718d36ce04acbaa19946575fcacb (patch) | |
| tree | c47b49354a5a3da76446b06c9d6fcc207d6f1248 | |
| parent | 4202d78df0bb056f3036b5c9bc789a10148a22c8 (diff) | |
| download | ghdl-410178f09ab8718d36ce04acbaa19946575fcacb.tar.gz ghdl-410178f09ab8718d36ce04acbaa19946575fcacb.tar.bz2 ghdl-410178f09ab8718d36ce04acbaa19946575fcacb.zip | |
synth: add support for integer rem.
| -rw-r--r-- | src/synth/netlists-builders.adb | 3 | ||||
| -rw-r--r-- | src/synth/netlists-disp_vhdl.adb | 6 | ||||
| -rw-r--r-- | src/synth/netlists-gates.ads | 3 | ||||
| -rw-r--r-- | src/synth/synth-oper.adb | 3 |
4 files changed, 12 insertions, 3 deletions
diff --git a/src/synth/netlists-builders.adb b/src/synth/netlists-builders.adb index e0c749792..7d885a9f6 100644 --- a/src/synth/netlists-builders.adb +++ b/src/synth/netlists-builders.adb @@ -432,6 +432,9 @@ package body Netlists.Builders is Create_Dyadic_Module (Design, Res.M_Dyadic (Id_Smod), Get_Identifier ("smod"), Id_Smod); + Create_Dyadic_Module (Design, Res.M_Dyadic (Id_Srem), + Get_Identifier ("srem"), Id_Srem); + Create_Dyadic_Module (Design, Res.M_Shift_Rotate (Id_Lsl), Get_Identifier ("lsl"), Id_Lsl); Create_Dyadic_Module (Design, Res.M_Shift_Rotate (Id_Lsr), diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb index b2bba0972..64eb85044 100644 --- a/src/synth/netlists-disp_vhdl.adb +++ b/src/synth/netlists-disp_vhdl.adb @@ -682,6 +682,12 @@ package body Netlists.Disp_Vhdl is Disp_Template (" \o0 <= std_logic_vector (resize (\si0 * \si1, \n0));" & NL, Inst, (0 => Get_Width (Get_Output (Inst, 0)))); + when Id_Smod => + Disp_Template + (" \o0 <= std_logic_vector (\si0 mod \si1);" & NL, Inst); + when Id_Srem => + Disp_Template + (" \o0 <= std_logic_vector (\si0 rem \si1);" & NL, Inst); when Id_Ult => Disp_Template (" \o0 <= '1' when \ui0 < \ui1 else '0';" & NL, Inst); diff --git a/src/synth/netlists-gates.ads b/src/synth/netlists-gates.ads index f45313e10..9e9260808 100644 --- a/src/synth/netlists-gates.ads +++ b/src/synth/netlists-gates.ads @@ -39,8 +39,9 @@ package Netlists.Gates is Id_Sdiv : constant Module_Id := 14; Id_Umod : constant Module_Id := 15; Id_Smod : constant Module_Id := 16; + Id_Srem : constant Module_Id := 17; - subtype Dyadic_Module_Id is Module_Id range Id_And .. Id_Smod; + subtype Dyadic_Module_Id is Module_Id range Id_And .. Id_Srem; -- Logical and arithmetic shifts. -- FIXME: clarify right operand: width, large values diff --git a/src/synth/synth-oper.adb b/src/synth/synth-oper.adb index 865326e95..8bc84df49 100644 --- a/src/synth/synth-oper.adb +++ b/src/synth/synth-oper.adb @@ -682,8 +682,7 @@ package body Synth.Oper is (Left.Scal rem Right.Scal, Get_Value_Type (Syn_Inst, Get_Type (Expr))); else - Error_Msg_Synth (+Expr, "non-constant rem not supported"); - return null; + return Synth_Int_Dyadic (Id_Srem); end if; when Iir_Predefined_Integer_Exp => if Is_Const (Left) and then Is_Const (Right) then |