testsuite/gna: add a test for #2346

6 files changed, 129 insertions, 0 deletions

diff --git a/testsuite/gna/issue2346/aggr.vhdl b/testsuite/gna/issue2346/aggr.vhdl
new file mode 100644
index 000000000..c9f0f0add
--- /dev/null
+++ b/testsuite/gna/issue2346/aggr.vhdl
@@ -0,0 +1,32 @@
+library ieee ;
+  use ieee.std_logic_1164.all ;
+  use ieee.numeric_std_unsigned.all ;
+
+entity AggregateWithDelay is
+end AggregateWithDelay ;
+architecture test of AggregateWithDelay is
+  constant tpd         : time := 1 ns ;
+  signal Clk           : std_logic := '0' ;
+  signal A1, A0  : std_logic ;
+begin
+
+  Clk <= not Clk after 5 ns ; 
+
+  DriveDataProc : process
+    variable A : std_logic_vector(1 downto 0) ; 
+  begin
+    wait until Clk = '1';
+
+    for i in 7 downto 0 loop
+      (A1, A0) <= to_slv(i, 2) after tpd ;
+-- The following is the work around
+--      A := to_slv(i, 2) ;
+--     A1 <= A(1) after tpd ;
+--     A0 <= A(0) after tpd ;
+      wait until Clk = '1' ; 
+      wait until Clk = '1' ; 
+    end loop ;
+    std.env.stop ;
+    wait ;
+  end process ;
+end;
diff --git a/testsuite/gna/issue2346/aggr1.vhdl b/testsuite/gna/issue2346/aggr1.vhdl
new file mode 100644
index 000000000..7418f5d72
--- /dev/null
+++ b/testsuite/gna/issue2346/aggr1.vhdl
@@ -0,0 +1,13 @@
+entity aggr1 is
+end;
+
+architecture test of aggr1 is
+  constant tpd         : time := 1 ns ;
+  signal A1, A0  : bit ;
+  function f return bit_vector is
+  begin
+    return "010";
+  end f;
+begin
+  (A1, A0) <=  f after tpd; -- to_slv(i, 2) after tpd ;
+end;
diff --git a/testsuite/gna/issue2346/aggr2.vhdl b/testsuite/gna/issue2346/aggr2.vhdl
new file mode 100644
index 000000000..a8788cb08
--- /dev/null
+++ b/testsuite/gna/issue2346/aggr2.vhdl
@@ -0,0 +1,17 @@
+entity aggr2 is
+end;
+
+architecture test of aggr2 is
+  constant tpd         : time := 1 ns ;
+  signal A1, A0  : bit ;
+  function f return bit_vector is
+  begin
+    return "01";
+  end f;
+  procedure asgn (signal o : out bit_vector) is
+  begin
+    o <= f after tpd;
+  end asgn;
+begin
+  asgn (o (1) => A1, o(0) => A0);
+end;
diff --git a/testsuite/gna/issue2346/aggr3.vhdl b/testsuite/gna/issue2346/aggr3.vhdl
new file mode 100644
index 000000000..3758b1310
--- /dev/null
+++ b/testsuite/gna/issue2346/aggr3.vhdl
@@ -0,0 +1,26 @@
+entity aggr3 is
+end;
+
+architecture test of aggr3 is
+  constant tpd         : time := 1 ns ;
+  signal A1, A0  : bit ;
+  function f return bit_vector is
+  begin
+    return "01";
+  end f;
+  procedure asgn (signal o : out bit_vector) is
+  begin
+    wait for 1 ns;
+    o <= f after tpd;
+  end asgn;
+begin
+  process
+  begin
+    asgn (o (1) => A1, o(0) => A0);
+    wait for 1 ns;
+    assert a1 = '1';
+    assert a0 = '0';
+    report "done";
+    wait;
+  end process;
+end;
diff --git a/testsuite/gna/issue2346/aggr4.vhdl b/testsuite/gna/issue2346/aggr4.vhdl
new file mode 100644
index 000000000..4eee0095d
--- /dev/null
+++ b/testsuite/gna/issue2346/aggr4.vhdl
@@ -0,0 +1,19 @@
+entity aggr4 is
+end;
+
+architecture test of aggr4 is
+
+  signal A1, A0  : bit ;
+
+  function aand (signal v : bit_vector) return bit is
+    variable r : bit;
+  begin
+    r := '1';
+    for i in v'range loop
+      r := r and v (i);
+    end loop;
+    return r;
+  end aand;
+begin
+  a1 <= aand (v (1) => A1, v(0) => A0);
+end;
diff --git a/testsuite/gna/issue2346/testsuite.sh b/testsuite/gna/issue2346/testsuite.sh
new file mode 100755
index 000000000..212a4acd7
--- /dev/null
+++ b/testsuite/gna/issue2346/testsuite.sh
@@ -0,0 +1,22 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+analyze aggr.vhdl
+elab_simulate AggregateWithDelay
+
+analyze aggr4.vhdl
+elab_simulate aggr4
+
+clean
+
+analyze aggr2.vhdl
+elab_simulate aggr2
+
+analyze aggr3.vhdl
+elab_simulate aggr3
+
+clean
+
+echo "Test successful"