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author | Tristan Gingold <tgingold@free.fr> | 2021-04-03 16:49:35 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2021-04-03 16:49:35 +0200 |
commit | 42a3bac62c95221096996dfbbbeabb0474130042 (patch) | |
tree | 486d4b10689e23b2c14d254fd731a38fb780465c | |
parent | 6617613f93e70df2e2b964f380652ea43e2bb2a5 (diff) | |
download | ghdl-42a3bac62c95221096996dfbbbeabb0474130042.tar.gz ghdl-42a3bac62c95221096996dfbbbeabb0474130042.tar.bz2 ghdl-42a3bac62c95221096996dfbbbeabb0474130042.zip |
testsuite/gna: add a test for #1708
-rw-r--r-- | testsuite/gna/issue1708/tb_top.vhdl | 34 | ||||
-rwxr-xr-x | testsuite/gna/issue1708/testsuite.sh | 10 |
2 files changed, 44 insertions, 0 deletions
diff --git a/testsuite/gna/issue1708/tb_top.vhdl b/testsuite/gna/issue1708/tb_top.vhdl new file mode 100644 index 000000000..274cf3872 --- /dev/null +++ b/testsuite/gna/issue1708/tb_top.vhdl @@ -0,0 +1,34 @@ +Library ieee; +use ieee.std_logic_1164.all; + +entity tb_top is +end entity; + + +architecture tb of tb_top is + + signal a,b : std_logic := '0'; + signal clk_sys : std_logic; + + default clock is rising_edge(clk_sys); +begin + + gen_clock_proc : process + begin + clk_sys <= '1'; + wait for 5 ns; + clk_sys <= '0'; + wait for 5 ns; + end process; + + test_proc : process + begin + a <= '1'; + wait for 50 ns; + std.env.finish; + end process; + + + my_seq : assert never {a = '1'; b = '1'}[=3]; + +end architecture tb; diff --git a/testsuite/gna/issue1708/testsuite.sh b/testsuite/gna/issue1708/testsuite.sh new file mode 100755 index 000000000..cafddf06e --- /dev/null +++ b/testsuite/gna/issue1708/testsuite.sh @@ -0,0 +1,10 @@ +#! /bin/sh + +. ../../testenv.sh + +export GHDL_STD_FLAGS=--std=08 +analyze_failure tb_top.vhdl + +clean + +echo "Test successful" |