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authorTristan Gingold <tgingold@free.fr>2016-10-01 06:50:34 +0200
committerTristan Gingold <tgingold@free.fr>2016-10-01 06:50:34 +0200
commit44095bf454b98b580ff41c92da52ce431a45828d (patch)
tree173ebcb253ca65151fc83f547861ce6e40f2b16f
parent2171004f8c93ed6edafe3096db70e1379b820c52 (diff)
downloadghdl-44095bf454b98b580ff41c92da52ce431a45828d.tar.gz
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Emit error message during analysis for missing generic association.
-rw-r--r--src/vhdl/sem.adb11
-rw-r--r--src/vhdl/translate/trans-chap5.adb1
-rwxr-xr-xtestsuite/gna/bug18361/testsuite.sh3
3 files changed, 6 insertions, 9 deletions
diff --git a/src/vhdl/sem.adb b/src/vhdl/sem.adb
index 66e81d135..9e57ec0e2 100644
--- a/src/vhdl/sem.adb
+++ b/src/vhdl/sem.adb
@@ -378,13 +378,10 @@ package body Sem is
-- GHDL: for a direct instantiation, follow rules of
-- LRM 1.1.1.1 Generic and LRM 1.1.1.2 Ports.
- if Flags.Vhdl_Std = Vhdl_87
- or else Get_Kind (Inter_Parent) = Iir_Kind_Entity_Declaration
- then
- Miss := Missing_Generic;
- else
- Miss := Missing_Allowed;
- end if;
+ -- The difference between 87 and 93 is simply a clarification:
+ -- missing association are left open, but need a default
+ -- expression in the formal declaration.
+ Miss := Missing_Generic;
when Iir_Kind_Binding_Indication =>
-- LRM 5.2.1.2 Generic map and port map aspects
Miss := Missing_Allowed;
diff --git a/src/vhdl/translate/trans-chap5.adb b/src/vhdl/translate/trans-chap5.adb
index c86f34602..f6a11be0f 100644
--- a/src/vhdl/translate/trans-chap5.adb
+++ b/src/vhdl/translate/trans-chap5.adb
@@ -742,6 +742,7 @@ package body Trans.Chap5 is
declare
Value : constant Iir := Get_Default_Value (Formal);
begin
+ pragma Assert (Is_Valid (Value));
Set_Map_Env (Formal_Env);
Chap4.Elab_Object_Value (Formal, Value);
Chap9.Destroy_Types (Value);
diff --git a/testsuite/gna/bug18361/testsuite.sh b/testsuite/gna/bug18361/testsuite.sh
index 94d709bb0..dac7090c1 100755
--- a/testsuite/gna/bug18361/testsuite.sh
+++ b/testsuite/gna/bug18361/testsuite.sh
@@ -2,8 +2,7 @@
. ../../testenv.sh
-analyze cnt.vhdl
-elab_simulate_failure cnt_v_tb
+analyze_failure cnt.vhdl
clean