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| author | Tristan Gingold <tgingold@free.fr> | 2019-08-20 04:54:29 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-08-20 04:54:29 +0200 |
| commit | 47b4650272ce425223da826b0de5bb7286036168 (patch) | |
| tree | 3778ae11ddea6e8f5bc69909a724f11029e35573 | |
| parent | b77eb1a27fa6838c7194a44f8d872005d08e6ac7 (diff) | |
| download | ghdl-47b4650272ce425223da826b0de5bb7286036168.tar.gz ghdl-47b4650272ce425223da826b0de5bb7286036168.tar.bz2 ghdl-47b4650272ce425223da826b0de5bb7286036168.zip | |
vhdl: handle assume in verification units.
| -rw-r--r-- | src/synth/synth-stmts.adb | 2 | ||||
| -rw-r--r-- | src/vhdl/vhdl-annotations.adb | 3 | ||||
| -rw-r--r-- | src/vhdl/vhdl-canon.adb | 2 | ||||
| -rw-r--r-- | src/vhdl/vhdl-parse.adb | 3 | ||||
| -rw-r--r-- | src/vhdl/vhdl-sem_psl.adb | 2 |
5 files changed, 11 insertions, 1 deletions
diff --git a/src/synth/synth-stmts.adb b/src/synth/synth-stmts.adb index 339c0a823..0d2c8bf9f 100644 --- a/src/synth/synth-stmts.adb +++ b/src/synth/synth-stmts.adb @@ -1652,6 +1652,8 @@ package body Synth.Stmts is null; when Iir_Kind_Psl_Assert_Directive => Synth_Psl_Assert_Directive (Syn_Inst, Item); + when Iir_Kind_Psl_Assume_Directive => + Synth_Psl_Assume_Directive (Syn_Inst, Item); when others => Error_Kind ("synth_verification_unit", Item); end case; diff --git a/src/vhdl/vhdl-annotations.adb b/src/vhdl/vhdl-annotations.adb index d3d959da6..b23e4b6e6 100644 --- a/src/vhdl/vhdl-annotations.adb +++ b/src/vhdl/vhdl-annotations.adb @@ -1165,7 +1165,8 @@ package body Vhdl.Annotations is case Get_Kind (Item) is when Iir_Kind_Psl_Default_Clock => null; - when Iir_Kind_Psl_Assert_Directive => + when Iir_Kind_Psl_Assert_Directive + | Iir_Kind_Psl_Assume_Directive => null; when others => Error_Kind ("annotate_vunit_declaration", Item); diff --git a/src/vhdl/vhdl-canon.adb b/src/vhdl/vhdl-canon.adb index 02818ad39..487edfb44 100644 --- a/src/vhdl/vhdl-canon.adb +++ b/src/vhdl/vhdl-canon.adb @@ -3239,6 +3239,8 @@ package body Vhdl.Canon is null; when Iir_Kind_Psl_Assert_Directive => Canon_Psl_Assert_Directive (Item); + when Iir_Kind_Psl_Assume_Directive => + Canon_Psl_Property_Directive (Item); when others => Error_Kind ("canon_psl_verification_unit", Item); end case; diff --git a/src/vhdl/vhdl-parse.adb b/src/vhdl/vhdl-parse.adb index 95c479a57..1983409a5 100644 --- a/src/vhdl/vhdl-parse.adb +++ b/src/vhdl/vhdl-parse.adb @@ -8630,6 +8630,7 @@ package body Vhdl.Parse is Res : Iir; begin Res := Create_Iir (Iir_Kind_Psl_Assume_Directive); + Set_Location (Res); -- Accept PSL tokens Vhdl.Scanner.Flag_Psl := True; @@ -9821,6 +9822,8 @@ package body Vhdl.Parse is case Current_Token is when Tok_Default => Item := Parse_Psl_Default_Clock (True); + when Tok_Assume => + Item := Parse_Psl_Assume_Directive (True); when Tok_Assert => Item := Parse_Psl_Assert_Directive (True); when others => diff --git a/src/vhdl/vhdl-sem_psl.adb b/src/vhdl/vhdl-sem_psl.adb index 917f35e97..b99ee5a17 100644 --- a/src/vhdl/vhdl-sem_psl.adb +++ b/src/vhdl/vhdl-sem_psl.adb @@ -952,6 +952,8 @@ package body Vhdl.Sem_Psl is Sem_Psl_Default_Clock (Item); when Iir_Kind_Psl_Assert_Directive => Item := Sem_Psl_Assert_Directive (Item, False); + when Iir_Kind_Psl_Assume_Directive => + Sem_Psl_Assume_Directive (Item); when others => Error_Kind ("sem_psl_verification_unit", Item); end case; |