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authorTristan Gingold <tgingold@free.fr>2019-10-08 18:51:23 +0200
committerTristan Gingold <tgingold@free.fr>2019-10-08 18:51:23 +0200
commit4bd6d595d65458e4cf56d8e896092757bb544e0b (patch)
treedb0b0781730c0cfca5d761239033c2080b24b5b7
parent561b15d8066fcaa2147b7e95d9e2bcc7044c7f36 (diff)
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testsuite/synth: add tests for previous commit.
Diffstat
-rw-r--r--testsuite/synth/arr01/arr05.vhdl46
-rw-r--r--testsuite/synth/arr01/arr06.vhdl45
-rw-r--r--testsuite/synth/arr01/arr07.vhdl45
-rw-r--r--testsuite/synth/arr01/tb_arr05.vhdl55
-rw-r--r--testsuite/synth/arr01/tb_arr06.vhdl55
-rw-r--r--testsuite/synth/arr01/tb_arr07.vhdl51
-rwxr-xr-xtestsuite/synth/arr01/testsuite.sh2
7 files changed, 298 insertions, 1 deletions
diff --git a/testsuite/synth/arr01/arr05.vhdl b/testsuite/synth/arr01/arr05.vhdl
new file mode 100644
index 000000000..f95dd7068
--- /dev/null
+++ b/testsuite/synth/arr01/arr05.vhdl
@@ -0,0 +1,46 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity arr05 is
+ port (clk : in std_logic;
+ val : std_logic_vector(7 downto 0);
+ res : out std_logic_vector(7 downto 0);
+ par : out std_logic);
+end arr05;
+
+architecture behav of arr05 is
+ type pipe_el is record
+ val : std_logic_vector(7 downto 0);
+ odd : std_logic;
+ end record;
+
+ type pipe_arr is array (0 to 4) of pipe_el;
+
+ type pipe_type is record
+ p : pipe_arr;
+ end record;
+
+ signal mem : pipe_type;
+ signal n_mem : pipe_type;
+ signal tick : std_logic := '0';
+begin
+ process(clk)
+ begin
+ if rising_edge (clk) then
+ mem <= n_mem;
+ tick <= not tick;
+ end if;
+ end process;
+
+ process(mem, val, tick)
+ begin
+ for i in 1 to pipe_arr'high loop
+ n_mem.p (i) <= mem.p (i - 1);
+ end loop;
+ n_mem.p (0).val <= val;
+ n_mem.p (0).odd <= tick;
+ end process;
+
+ res <= mem.p (pipe_arr'high).val;
+ par <= mem.p (pipe_arr'high).odd;
+end behav;
diff --git a/testsuite/synth/arr01/arr06.vhdl b/testsuite/synth/arr01/arr06.vhdl
new file mode 100644
index 000000000..6ba91df88
--- /dev/null
+++ b/testsuite/synth/arr01/arr06.vhdl
@@ -0,0 +1,45 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity arr06 is
+ port (clk : in std_logic;
+ val : std_logic_vector(7 downto 0);
+ res : out std_logic_vector(7 downto 0);
+ par : out std_logic);
+end arr06;
+
+architecture behav of arr06 is
+ type pipe_el is record
+ val : std_logic_vector(7 downto 0);
+ odd : std_logic;
+ end record;
+
+ type pipe_type is array (0 to 4) of pipe_el;
+
+ signal mem : pipe_type;
+ signal n_mem : pipe_type;
+ signal tick : std_logic := '0';
+begin
+ process(clk)
+ begin
+ if rising_edge (clk) then
+ mem <= n_mem;
+ tick <= not tick;
+ end if;
+ end process;
+
+ process(mem, val, tick)
+ variable v : pipe_type;
+ begin
+ for i in 1 to pipe_type'high loop
+ v (i) := mem (i - 1);
+ end loop;
+ v (0).val := val;
+ v (0).odd := tick;
+
+ n_mem <= v;
+ end process;
+
+ res <= mem (pipe_type'high).val;
+ par <= mem (pipe_type'high).odd;
+end behav;
diff --git a/testsuite/synth/arr01/arr07.vhdl b/testsuite/synth/arr01/arr07.vhdl
new file mode 100644
index 000000000..5c4c89fa5
--- /dev/null
+++ b/testsuite/synth/arr01/arr07.vhdl
@@ -0,0 +1,45 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity arr07 is
+ port (clk : in std_logic;
+ val : std_logic_vector(7 downto 0);
+ res : out std_logic_vector(7 downto 0);
+ par : out std_logic);
+end arr07;
+
+architecture behav of arr07 is
+ type pipe_el is record
+ val : std_logic_vector(7 downto 0);
+ odd : std_logic;
+ end record;
+
+ type pipe_type is array (0 to 15) of pipe_el;
+
+ signal mem : pipe_type;
+ signal n_mem : pipe_type;
+ signal tick : std_logic := '0';
+begin
+ process(clk)
+ begin
+ if rising_edge (clk) then
+ mem <= n_mem;
+ tick <= not tick;
+ end if;
+ end process;
+
+ process(mem, val, tick)
+ variable v : pipe_type;
+ begin
+ for i in 1 to pipe_type'high loop
+ v (i) := mem (i - 1);
+ end loop;
+ v (0).val := val;
+ v (0).odd := tick;
+
+ n_mem <= v;
+ end process;
+
+ res <= mem (pipe_type'high).val;
+ par <= mem (pipe_type'high).odd;
+end behav;
diff --git a/testsuite/synth/arr01/tb_arr05.vhdl b/testsuite/synth/arr01/tb_arr05.vhdl
new file mode 100644
index 000000000..d9ab0d5dd
--- /dev/null
+++ b/testsuite/synth/arr01/tb_arr05.vhdl
@@ -0,0 +1,55 @@
+entity tb_arr05 is
+end tb_arr05;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_arr05 is
+ signal clk : std_logic;
+ signal val : std_logic_vector(7 downto 0);
+ signal res : std_logic_vector(7 downto 0);
+ signal par : std_logic;
+begin
+ dut: entity work.arr05
+ port map (clk => clk, val => val, res => res, par => par);
+
+ process
+ procedure pulse is
+ begin
+ clk <= '0';
+ wait for 1 ns;
+ clk <= '1';
+ wait for 1 ns;
+ end pulse;
+ begin
+ val <= x"a0";
+ pulse;
+ val <= x"71";
+ pulse;
+ val <= x"82";
+ pulse;
+ val <= x"23";
+ pulse;
+ val <= x"fe";
+ pulse;
+ assert res = x"a0" severity failure;
+
+ val <= x"e4";
+ pulse;
+ assert res = x"71" severity failure;
+
+ val <= x"c5";
+ pulse;
+ assert res = x"82" severity failure;
+
+ val <= x"f6";
+ pulse;
+ assert res = x"23" severity failure;
+
+ val <= x"57";
+ pulse;
+ assert res = x"fe" severity failure;
+
+ wait;
+ end process;
+end behav;
diff --git a/testsuite/synth/arr01/tb_arr06.vhdl b/testsuite/synth/arr01/tb_arr06.vhdl
new file mode 100644
index 000000000..27b3610e4
--- /dev/null
+++ b/testsuite/synth/arr01/tb_arr06.vhdl
@@ -0,0 +1,55 @@
+entity tb_arr06 is
+end tb_arr06;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_arr06 is
+ signal clk : std_logic;
+ signal val : std_logic_vector(7 downto 0);
+ signal res : std_logic_vector(7 downto 0);
+ signal par : std_logic;
+begin
+ dut: entity work.arr06
+ port map (clk => clk, val => val, res => res, par => par);
+
+ process
+ procedure pulse is
+ begin
+ clk <= '0';
+ wait for 1 ns;
+ clk <= '1';
+ wait for 1 ns;
+ end pulse;
+ begin
+ val <= x"a0";
+ pulse;
+ val <= x"71";
+ pulse;
+ val <= x"82";
+ pulse;
+ val <= x"23";
+ pulse;
+ val <= x"fe";
+ pulse;
+ assert res = x"a0" severity failure;
+
+ val <= x"e4";
+ pulse;
+ assert res = x"71" severity failure;
+
+ val <= x"c5";
+ pulse;
+ assert res = x"82" severity failure;
+
+ val <= x"f6";
+ pulse;
+ assert res = x"23" severity failure;
+
+ val <= x"57";
+ pulse;
+ assert res = x"fe" severity failure;
+
+ wait;
+ end process;
+end behav;
diff --git a/testsuite/synth/arr01/tb_arr07.vhdl b/testsuite/synth/arr01/tb_arr07.vhdl
new file mode 100644
index 000000000..3e461ffdb
--- /dev/null
+++ b/testsuite/synth/arr01/tb_arr07.vhdl
@@ -0,0 +1,51 @@
+entity tb_arr07 is
+end tb_arr07;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+architecture behav of tb_arr07 is
+ signal clk : std_logic;
+ signal val : std_logic_vector(7 downto 0);
+ signal res : std_logic_vector(7 downto 0);
+ signal par : std_logic;
+begin
+ dut: entity work.arr07
+ port map (clk => clk, val => val, res => res, par => par);
+
+ process
+ procedure pulse is
+ begin
+ clk <= '0';
+ wait for 1 ns;
+ clk <= '1';
+ wait for 1 ns;
+ end pulse;
+ begin
+ for i in 0 to 15 loop
+ val <= std_logic_vector (to_unsigned(i, 4) & to_unsigned (15 - i, 4));
+ pulse;
+ end loop;
+
+ assert res = x"0f" severity failure;
+
+ val <= x"e4";
+ pulse;
+ assert res = x"1e" severity failure;
+
+ val <= x"c5";
+ pulse;
+ assert res = x"2d" severity failure;
+
+ val <= x"f6";
+ pulse;
+ assert res = x"3c" severity failure;
+
+ val <= x"57";
+ pulse;
+ assert res = x"4b" severity failure;
+
+ wait;
+ end process;
+end behav;
diff --git a/testsuite/synth/arr01/testsuite.sh b/testsuite/synth/arr01/testsuite.sh
index 53b3a9116..71b198348 100755
--- a/testsuite/synth/arr01/testsuite.sh
+++ b/testsuite/synth/arr01/testsuite.sh
@@ -2,7 +2,7 @@
. ../../testenv.sh
-for t in arr01 arr02 arr04; do
+for t in arr01 arr02 arr04 arr05 arr06 arr07; do
analyze $t.vhdl tb_$t.vhdl
elab_simulate tb_$t
clean
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-14 22:59:32 +0000