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| author | Tristan Gingold <tgingold@free.fr> | 2022-08-04 08:56:18 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-08-04 08:56:18 +0200 |
| commit | 4ce5f0c046685ad630f9eb6140e87a66be020f94 (patch) | |
| tree | 7c00ed2789c1c1e4dbf8c0c4f6c96c3ab197bcb9 | |
| parent | bba4c415f1742478fed72fb8fc3017dda0abb156 (diff) | |
| download | ghdl-4ce5f0c046685ad630f9eb6140e87a66be020f94.tar.gz ghdl-4ce5f0c046685ad630f9eb6140e87a66be020f94.tar.bz2 ghdl-4ce5f0c046685ad630f9eb6140e87a66be020f94.zip | |
synth-vhdl_oper: remove check for positive rotation amount. Fix #2159
| -rw-r--r-- | src/synth/synth-vhdl_oper.adb | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/src/synth/synth-vhdl_oper.adb b/src/synth/synth-vhdl_oper.adb index 274306245..9cc3f5e95 100644 --- a/src/synth/synth-vhdl_oper.adb +++ b/src/synth/synth-vhdl_oper.adb @@ -699,10 +699,8 @@ package body Synth.Vhdl_Oper is Amt := Amt mod Int64 (Left.Typ.W); R1 := Build_Const_UB32 (Ctxt, Uns32 (Amt), Right.Typ.W); Set_Location (R1, Right_Expr); - elsif not Is_Positive (Right) then - Error_Msg_Synth (+Expr, "rotation quantity must be unsigned"); - return Left; else + -- The amount should be positive. R1 := Get_Net (Ctxt, Right); Ww := Netlists.Utils.Clog2 (Left.Typ.W); if Right.Typ.W >= Ww then |