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author | Tristan Gingold <tgingold@free.fr> | 2021-09-22 19:41:34 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2021-09-23 04:43:13 +0200 |
commit | 4cee5eeae85beb7432c8e085da0a5bf8aa1db8a1 (patch) | |
tree | 7908d67a9f19f6e9f3766dd4967baff669cda9c3 | |
parent | 565967d1328237bea7da40b99efd03ac1f326abd (diff) | |
download | ghdl-4cee5eeae85beb7432c8e085da0a5bf8aa1db8a1.tar.gz ghdl-4cee5eeae85beb7432c8e085da0a5bf8aa1db8a1.tar.bz2 ghdl-4cee5eeae85beb7432c8e085da0a5bf8aa1db8a1.zip |
testsuite/gna: add a test for #1875
-rw-r--r-- | testsuite/gna/issue1875/test.vhdl | 19 | ||||
-rwxr-xr-x | testsuite/gna/issue1875/testsuite.sh | 11 |
2 files changed, 30 insertions, 0 deletions
diff --git a/testsuite/gna/issue1875/test.vhdl b/testsuite/gna/issue1875/test.vhdl new file mode 100644 index 000000000..e1540e551 --- /dev/null +++ b/testsuite/gna/issue1875/test.vhdl @@ -0,0 +1,19 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.VITAL_timing.all; +use IEEE.VITAL_primitives.all; + +entity test is + port ( + CLK : in std_logic_vector(1 downto 0) + ); + attribute VITAL_LEVEL0 of test : entity is TRUE; +end test; + +architecture VITAL_ACT of test is +begin + process + begin + wait; + end process; +end architecture; diff --git a/testsuite/gna/issue1875/testsuite.sh b/testsuite/gna/issue1875/testsuite.sh new file mode 100755 index 000000000..a3abac41b --- /dev/null +++ b/testsuite/gna/issue1875/testsuite.sh @@ -0,0 +1,11 @@ +#! /bin/sh + +. ../../testenv.sh + +export GHDL_STD_FLAGS="--std=08 -frelaxed" +analyze test.vhdl +elab_simulate test + +clean + +echo "Test successful" |