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authorTristan Gingold <tgingold@free.fr>2022-07-25 08:04:59 +0200
committerTristan Gingold <tgingold@free.fr>2022-07-25 08:04:59 +0200
commit50f95f658d69d7c3ab1369e14ac64e3f6bf0bd0e (patch)
tree3657b98951d9376f45f77e2fbfd6127a4db280d8
parent9113c965378a69447386d57d6d8a9f4caf7d1581 (diff)
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vhdl-canon: handle conditional variable assignment. Fix #2138
-rw-r--r--src/vhdl/vhdl-canon.adb17
1 files changed, 16 insertions, 1 deletions
diff --git a/src/vhdl/vhdl-canon.adb b/src/vhdl/vhdl-canon.adb
index 0f2b2a494..edddfc721 100644
--- a/src/vhdl/vhdl-canon.adb
+++ b/src/vhdl/vhdl-canon.adb
@@ -477,6 +477,22 @@ package body Vhdl.Canon is
(Get_Target (Stmt), List, True);
Canon_Extract_Sensitivity_Expression
(Get_Expression (Stmt), List, False);
+ when Iir_Kind_Conditional_Variable_Assignment_Statement =>
+ declare
+ Ce : Iir;
+ begin
+ Canon_Extract_Sensitivity_Expression
+ (Get_Target (Stmt), List, True);
+ Ce := Get_Conditional_Expression_Chain (Stmt);
+ while Ce /= Null_Iir loop
+ Canon_Extract_Sensitivity_Expression
+ (Get_Condition (Ce), List, False);
+ Canon_Extract_Sensitivity_Expression
+ (Get_Expression (Ce), List, False);
+ Ce := Get_Chain (Ce);
+ end loop;
+ end;
+
when Iir_Kind_Simple_Signal_Assignment_Statement =>
-- LRM08 11.3
-- See variable assignment statement case.
@@ -560,7 +576,6 @@ package body Vhdl.Canon is
Canon_Extract_Sensitivity_Procedure_Call
(Get_Procedure_Call (Stmt), List);
when Iir_Kind_Selected_Waveform_Assignment_Statement
- | Iir_Kind_Conditional_Variable_Assignment_Statement
| Iir_Kind_Signal_Force_Assignment_Statement
| Iir_Kind_Signal_Release_Assignment_Statement
| Iir_Kind_Break_Statement