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authorTristan Gingold <tgingold@free.fr>2020-02-11 18:30:44 +0100
committerTristan Gingold <tgingold@free.fr>2020-02-11 18:30:44 +0100
commit568b3a849e6a4e8ebadbd21ca0f41e646a4b9c3d (patch)
treeecd74c9f630a4176b65cabf3d7856a10eef54e5b
parent0605f04fb3a0dbbf7d78d6478a5652b890acec0f (diff)
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testsuite/synth: add test for #1132
-rw-r--r--testsuite/synth/issue1132/bar.vhdl22
-rwxr-xr-xtestsuite/synth/issue1132/testsuite.sh12
2 files changed, 34 insertions, 0 deletions
diff --git a/testsuite/synth/issue1132/bar.vhdl b/testsuite/synth/issue1132/bar.vhdl
new file mode 100644
index 000000000..17aa50732
--- /dev/null
+++ b/testsuite/synth/issue1132/bar.vhdl
@@ -0,0 +1,22 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity bar is
+ port (
+ clk : in std_logic;
+ input : in unsigned(7 downto 0);
+ output_a : out unsigned(7 downto 0);
+ output_b : out unsigned(7 downto 0)
+ );
+end bar;
+
+architecture bar of bar is
+
+begin
+
+ output_a <= 10 + input;
+ -- This works as expected
+ output_b <= input + 10;
+
+end bar;
diff --git a/testsuite/synth/issue1132/testsuite.sh b/testsuite/synth/issue1132/testsuite.sh
new file mode 100755
index 000000000..c118fa784
--- /dev/null
+++ b/testsuite/synth/issue1132/testsuite.sh
@@ -0,0 +1,12 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in bar; do
+ synth $t.vhdl -e $t > syn_$t.vhdl
+ analyze syn_$t.vhdl
+done
+
+clean
+
+echo "Test successful"