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author | Tristan Gingold <tgingold@free.fr> | 2023-02-09 07:54:53 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2023-02-09 07:54:53 +0100 |
commit | 5bb3160559d2180f6300e21cf5bd853b63b32d37 (patch) | |
tree | db79e20e79c926ac1ad6c8836f2f0f4cdb5b31fb | |
parent | d1ff79789a621a485aeb4c854ce136c9f6a8ff70 (diff) | |
download | ghdl-5bb3160559d2180f6300e21cf5bd853b63b32d37.tar.gz ghdl-5bb3160559d2180f6300e21cf5bd853b63b32d37.tar.bz2 ghdl-5bb3160559d2180f6300e21cf5bd853b63b32d37.zip |
testsuite/synth: add a test for #2347
-rw-r--r-- | testsuite/synth/issue2347/ent.vhdl | 41 | ||||
-rwxr-xr-x | testsuite/synth/issue2347/testsuite.sh | 8 |
2 files changed, 49 insertions, 0 deletions
diff --git a/testsuite/synth/issue2347/ent.vhdl b/testsuite/synth/issue2347/ent.vhdl new file mode 100644 index 000000000..2cefd5472 --- /dev/null +++ b/testsuite/synth/issue2347/ent.vhdl @@ -0,0 +1,41 @@ +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +LIBRARY work; + +ENTITY ent IS + + PORT (not_reset : IN STD_LOGIC; + clock : IN STD_LOGIC; + inp : IN integer; + outp : OUT STD_LOGIC_VECTOR(31 downto 0)); +END ent ; + +ARCHITECTURE rtl OF ent IS + + +BEGIN + + PROCESS (not_reset,clock) + BEGIN + + IF(not_reset='0') THEN + + outp <= CONV_STD_LOGIC_VECTOR(CONV_UNSIGNED(0,32),32); +-- outp <= STD_LOGIC_VECTOR(CONV_UNSIGNED(0,32)); + + ELSIF(clock'EVENT AND clock='1') THEN + + outp <= CONV_STD_LOGIC_VECTOR(CONV_UNSIGNED(inp,32),32); +-- outp <= STD_LOGIC_VECTOR(CONV_UNSIGNED(inp,32)); + + END IF; + + END PROCESS; + + +END rtl; + + diff --git a/testsuite/synth/issue2347/testsuite.sh b/testsuite/synth/issue2347/testsuite.sh new file mode 100755 index 000000000..f8d05daef --- /dev/null +++ b/testsuite/synth/issue2347/testsuite.sh @@ -0,0 +1,8 @@ +#! /bin/sh + +. ../../testenv.sh + +GHDL_STD_FLAGS=-fsynopsys +synth_only ent + +echo "Test successful" |