testsuite/synth: add a test for block declarations.

5 files changed, 141 insertions, 0 deletions

diff --git a/testsuite/synth/block01/block01.vhdl b/testsuite/synth/block01/block01.vhdl
new file mode 100644
index 000000000..40dc1c601
--- /dev/null
+++ b/testsuite/synth/block01/block01.vhdl
@@ -0,0 +1,21 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity block01 is
+  port (q : out std_logic;
+        d : std_logic;
+        clk : std_logic);
+end block01;
+
+architecture behav of block01 is
+begin
+  b1 : block
+  begin
+    process (clk) is
+    begin
+      if rising_edge (clk) then
+        q <= d;
+      end if;
+    end process;
+  end block b1;
+end behav;
diff --git a/testsuite/synth/block01/block02.vhdl b/testsuite/synth/block01/block02.vhdl
new file mode 100644
index 000000000..a22edae17
--- /dev/null
+++ b/testsuite/synth/block01/block02.vhdl
@@ -0,0 +1,24 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity block02 is
+  port (q : out std_logic;
+        d : std_logic;
+        clk : std_logic);
+end block02;
+
+architecture behav of block02 is
+begin
+  b1 : block
+    signal s : std_logic;
+  begin
+    process (clk) is
+    begin
+      if rising_edge (clk) then
+        s <= d;
+      end if;
+    end process;
+
+    q <= s;
+  end block b1;
+end behav;
diff --git a/testsuite/synth/block01/tb_block01.vhdl b/testsuite/synth/block01/tb_block01.vhdl
new file mode 100644
index 000000000..e04e60dc2
--- /dev/null
+++ b/testsuite/synth/block01/tb_block01.vhdl
@@ -0,0 +1,40 @@
+entity tb_block01 is
+end tb_block01;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_block01 is
+  signal clk : std_logic;
+  signal din : std_logic;
+  signal dout : std_logic;
+begin
+  dut: entity work.block01
+    port map (
+      q => dout,
+      d => din,
+      clk => clk);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    din <= '0';
+    pulse;
+    assert dout = '0' severity failure;
+    din <= '1';
+    pulse;
+    assert dout = '1' severity failure;
+    pulse;
+    assert dout = '1' severity failure;
+    din <= '0';
+    pulse;
+    assert dout = '0' severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/block01/tb_block02.vhdl b/testsuite/synth/block01/tb_block02.vhdl
new file mode 100644
index 000000000..31745b54d
--- /dev/null
+++ b/testsuite/synth/block01/tb_block02.vhdl
@@ -0,0 +1,40 @@
+entity tb_block02 is
+end tb_block02;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_block02 is
+  signal clk : std_logic;
+  signal din : std_logic;
+  signal dout : std_logic;
+begin
+  dut: entity work.block02
+    port map (
+      q => dout,
+      d => din,
+      clk => clk);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    din <= '0';
+    pulse;
+    assert dout = '0' severity failure;
+    din <= '1';
+    pulse;
+    assert dout = '1' severity failure;
+    pulse;
+    assert dout = '1' severity failure;
+    din <= '0';
+    pulse;
+    assert dout = '0' severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/block01/testsuite.sh b/testsuite/synth/block01/testsuite.sh
new file mode 100755
index 000000000..8729220fc
--- /dev/null
+++ b/testsuite/synth/block01/testsuite.sh
@@ -0,0 +1,16 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in block01 block02; do
+    analyze $t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+
+    synth $t.vhdl -e $t > syn_$t.vhdl
+    analyze syn_$t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+done
+
+echo "Test successful"