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authorTristan Gingold <tgingold@free.fr>2018-08-06 07:52:39 +0200
committerTristan Gingold <tgingold@free.fr>2018-08-07 06:27:17 +0200
commit5f3b43dcd3a63638f81a897ace8efa7c9e57d6a3 (patch)
treeede3bdf4024b5fb9debab8ce5aa789a4f77f6a8c
parentd62f20f969975166fc0a28198bb909ea0a7dec9a (diff)
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Add testcase for #615
-rw-r--r--testsuite/gna/issue615/repr.ghwbin0 -> 511 bytes
-rw-r--r--testsuite/gna/issue615/repr.vhdl17
-rwxr-xr-xtestsuite/gna/issue615/testsuite.sh16
3 files changed, 33 insertions, 0 deletions
diff --git a/testsuite/gna/issue615/repr.ghw b/testsuite/gna/issue615/repr.ghw
new file mode 100644
index 000000000..6756e01b9
--- /dev/null
+++ b/testsuite/gna/issue615/repr.ghw
Binary files differ
diff --git a/testsuite/gna/issue615/repr.vhdl b/testsuite/gna/issue615/repr.vhdl
new file mode 100644
index 000000000..ed8cf82d8
--- /dev/null
+++ b/testsuite/gna/issue615/repr.vhdl
@@ -0,0 +1,17 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity repr is
+end entity;
+
+architecture arch of repr is
+
+ constant CYCLE : time := 10 ns;
+
+ signal vec1 : std_logic_vector(31 downto 0);
+ signal vec2 : std_logic_vector(31 to 0);
+begin
+ vec1 <= (others => '0');
+ vec2 <= (others => '0');
+
+end arch;
diff --git a/testsuite/gna/issue615/testsuite.sh b/testsuite/gna/issue615/testsuite.sh
new file mode 100755
index 000000000..dfb9cc395
--- /dev/null
+++ b/testsuite/gna/issue615/testsuite.sh
@@ -0,0 +1,16 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+analyze repr.vhdl
+elab repr
+if ghdl_has_feature repr ghw; then
+ simulate repr --wave=repr.ghw
+# TODO: check with ghwdump ?
+fi
+
+
+clean
+
+echo "Test successful"