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author | Tristan Gingold <tgingold@free.fr> | 2020-03-22 08:41:16 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-03-22 08:41:16 +0100 |
commit | 600d8fad841f92c600c01d18569e9e4c6f843d21 (patch) | |
tree | 68f5f55f68ba0493fb1495b10bb6f357bcd7be98 | |
parent | 8a35846d7e91f26d22cb059cfbf21d9e5645314d (diff) | |
download | ghdl-600d8fad841f92c600c01d18569e9e4c6f843d21.tar.gz ghdl-600d8fad841f92c600c01d18569e9e4c6f843d21.tar.bz2 ghdl-600d8fad841f92c600c01d18569e9e4c6f843d21.zip |
synth: handle ieee.numeric_std.to_01
-rw-r--r-- | python/libghdl/thin/std_names.py | 389 | ||||
-rw-r--r-- | python/libghdl/thin/vhdl/nodes.py | 182 | ||||
-rw-r--r-- | src/std_names.adb | 3 | ||||
-rw-r--r-- | src/std_names.ads | 35 | ||||
-rw-r--r-- | src/synth/synth-oper.adb | 12 | ||||
-rw-r--r-- | src/vhdl/vhdl-ieee-numeric.adb | 25 | ||||
-rw-r--r-- | src/vhdl/vhdl-nodes.ads | 3 |
7 files changed, 343 insertions, 306 deletions
diff --git a/python/libghdl/thin/std_names.py b/python/libghdl/thin/std_names.py index 7f5f87617..b90bbd036 100644 --- a/python/libghdl/thin/std_names.py +++ b/python/libghdl/thin/std_names.py @@ -601,196 +601,199 @@ class Name: To_Stdlogicvector = 813 To_Stdulogicvector = 814 Is_X = 815 - Conv_Signed = 816 - Conv_Unsigned = 817 - Conv_Integer = 818 - Conv_Std_Logic_Vector = 819 - And_Reduce = 820 - Nand_Reduce = 821 - Or_Reduce = 822 - Nor_Reduce = 823 - Xor_Reduce = 824 - Xnor_Reduce = 825 - Ceil = 826 - Round = 827 - Log2 = 828 - Sin = 829 - Cos = 830 - Last_Ieee_Name = 830 - First_Synthesis = 831 - Allconst = 831 - Allseq = 832 - Anyconst = 833 - Anyseq = 834 - Last_Synthesis = 834 - First_Directive = 835 - Define = 835 - Endif = 836 - Ifdef = 837 - Ifndef = 838 - Include = 839 - Timescale = 840 - Undef = 841 - Protect = 842 - Begin_Protected = 843 - End_Protected = 844 - Key_Block = 845 - Data_Block = 846 - Line = 847 - Celldefine = 848 - Endcelldefine = 849 - Default_Nettype = 850 - Resetall = 851 - Last_Directive = 851 - First_Systask = 852 - Bits = 852 - D_Root = 853 - D_Unit = 854 - Last_Systask = 854 - First_SV_Method = 855 - Size = 855 - Insert = 856 - Delete = 857 - Pop_Front = 858 - Pop_Back = 859 - Push_Front = 860 - Push_Back = 861 - Name = 862 - Len = 863 - Substr = 864 - Exists = 865 - Atoi = 866 - Itoa = 867 - Find = 868 - Find_Index = 869 - Find_First = 870 - Find_First_Index = 871 - Find_Last = 872 - Find_Last_Index = 873 - Num = 874 - Randomize = 875 - Pre_Randomize = 876 - Post_Randomize = 877 - Srandom = 878 - Get_Randstate = 879 - Set_Randstate = 880 - Seed = 881 - State = 882 - Last_SV_Method = 882 - First_BSV = 883 - uAction = 883 - uActionValue = 884 - BVI = 885 - uC = 886 - uCF = 887 - uE = 888 - uSB = 889 - uSBR = 890 - Action = 891 - Endaction = 892 - Actionvalue = 893 - Endactionvalue = 894 - Ancestor = 895 - Clocked_By = 896 - Default_Clock = 897 - Default_Reset = 898 - Dependencies = 899 - Deriving = 900 - Determines = 901 - Enable = 902 - Ifc_Inout = 903 - Input_Clock = 904 - Input_Reset = 905 - Instance = 906 - Endinstance = 907 - Let = 908 - Match = 909 - Method = 910 - Endmethod = 911 - Numeric = 912 - Output_Clock = 913 - Output_Reset = 914 - Par = 915 - Endpar = 916 - Path = 917 - Provisos = 918 - Ready = 919 - Reset_By = 920 - Rule = 921 - Endrule = 922 - Rules = 923 - Endrules = 924 - Same_Family = 925 - Schedule = 926 - Seq = 927 - Endseq = 928 - Typeclass = 929 - Endtypeclass = 930 - Valueof = 931 - uValueof = 932 - Last_BSV = 932 - First_Comment = 933 - Psl = 933 - Pragma = 934 - Synthesis = 935 - Synopsys = 936 - Translate_Off = 937 - Translate_On = 938 - Last_Comment = 938 - First_PSL = 939 - A = 939 - Af = 940 - Ag = 941 - Ax = 942 - Abort = 943 - Assume_Guarantee = 944 - Before = 945 - Clock = 946 - E = 947 - Ef = 948 - Eg = 949 - Ex = 950 - Endpoint = 951 - Eventually = 952 - Fairness = 953 - Fell = 954 - Forall = 955 - G = 956 - Inf = 957 - Inherit = 958 - Never = 959 - Next_A = 960 - Next_E = 961 - Next_Event = 962 - Next_Event_A = 963 - Next_Event_E = 964 - Prev = 965 - Rose = 966 - Strong = 967 - W = 968 - Whilenot = 969 - Within = 970 - X = 971 - Last_PSL = 971 - First_Edif = 972 - Celltype = 982 - View = 983 - Viewtype = 984 - Direction = 985 - Contents = 986 - Net = 987 - Viewref = 988 - Cellref = 989 - Libraryref = 990 - Portinstance = 991 - Joined = 992 - Portref = 993 - Instanceref = 994 - Design = 995 - Designator = 996 - Owner = 997 - Member = 998 - Number = 999 - Rename = 1000 - Userdata = 1001 - Last_Edif = 1001 + To_01 = 816 + Conv_Signed = 817 + Conv_Unsigned = 818 + Conv_Integer = 819 + Conv_Std_Logic_Vector = 820 + And_Reduce = 821 + Nand_Reduce = 822 + Or_Reduce = 823 + Nor_Reduce = 824 + Xor_Reduce = 825 + Xnor_Reduce = 826 + Ceil = 827 + Round = 828 + Log2 = 829 + Sin = 830 + Cos = 831 + Last_Ieee_Name = 831 + First_Synthesis = 832 + Allconst = 832 + Allseq = 833 + Anyconst = 834 + Anyseq = 835 + Last_Synthesis = 835 + First_Directive = 836 + Define = 836 + Endif = 837 + Ifdef = 838 + Ifndef = 839 + Include = 840 + Timescale = 841 + Undef = 842 + Protect = 843 + Begin_Protected = 844 + End_Protected = 845 + Key_Block = 846 + Data_Block = 847 + Line = 848 + Celldefine = 849 + Endcelldefine = 850 + Default_Nettype = 851 + Resetall = 852 + Last_Directive = 852 + First_Systask = 853 + Bits = 853 + D_Root = 854 + D_Unit = 855 + Last_Systask = 855 + First_SV_Method = 856 + Size = 856 + Insert = 857 + Delete = 858 + Pop_Front = 859 + Pop_Back = 860 + Push_Front = 861 + Push_Back = 862 + Name = 863 + Len = 864 + Substr = 865 + Exists = 866 + Atoi = 867 + Itoa = 868 + Find = 869 + Find_Index = 870 + Find_First = 871 + Find_First_Index = 872 + Find_Last = 873 + Find_Last_Index = 874 + Num = 875 + Randomize = 876 + Pre_Randomize = 877 + Post_Randomize = 878 + Srandom = 879 + Get_Randstate = 880 + Set_Randstate = 881 + Seed = 882 + State = 883 + Last_SV_Method = 883 + First_BSV = 884 + uAction = 884 + uActionValue = 885 + BVI = 886 + uC = 887 + uCF = 888 + uE = 889 + uSB = 890 + uSBR = 891 + Action = 892 + Endaction = 893 + Actionvalue = 894 + Endactionvalue = 895 + Ancestor = 896 + Clocked_By = 897 + Default_Clock = 898 + Default_Reset = 899 + Dependencies = 900 + Deriving = 901 + Determines = 902 + Enable = 903 + Ifc_Inout = 904 + Input_Clock = 905 + Input_Reset = 906 + Instance = 907 + Endinstance = 908 + Let = 909 + Match = 910 + Method = 911 + Endmethod = 912 + Numeric = 913 + Output_Clock = 914 + Output_Reset = 915 + Par = 916 + Endpar = 917 + Path = 918 + Provisos = 919 + Ready = 920 + Reset_By = 921 + Rule = 922 + Endrule = 923 + Rules = 924 + Endrules = 925 + Same_Family = 926 + Schedule = 927 + Seq = 928 + Endseq = 929 + Typeclass = 930 + Endtypeclass = 931 + Valueof = 932 + uValueof = 933 + Last_BSV = 933 + First_Comment = 934 + Psl = 934 + Pragma = 935 + Synthesis = 936 + Synopsys = 937 + Translate_Off = 938 + Translate_On = 939 + Translate = 940 + Off = 941 + Last_Comment = 941 + First_PSL = 942 + A = 942 + Af = 943 + Ag = 944 + Ax = 945 + Abort = 946 + Assume_Guarantee = 947 + Before = 948 + Clock = 949 + E = 950 + Ef = 951 + Eg = 952 + Ex = 953 + Endpoint = 954 + Eventually = 955 + Fairness = 956 + Fell = 957 + Forall = 958 + G = 959 + Inf = 960 + Inherit = 961 + Never = 962 + Next_A = 963 + Next_E = 964 + Next_Event = 965 + Next_Event_A = 966 + Next_Event_E = 967 + Prev = 968 + Rose = 969 + Strong = 970 + W = 971 + Whilenot = 972 + Within = 973 + X = 974 + Last_PSL = 974 + First_Edif = 975 + Celltype = 985 + View = 986 + Viewtype = 987 + Direction = 988 + Contents = 989 + Net = 990 + Viewref = 991 + Cellref = 992 + Libraryref = 993 + Portinstance = 994 + Joined = 995 + Portref = 996 + Instanceref = 997 + Design = 998 + Designator = 999 + Owner = 1000 + Member = 1001 + Number = 1002 + Rename = 1003 + Userdata = 1004 + Last_Edif = 1004 diff --git a/python/libghdl/thin/vhdl/nodes.py b/python/libghdl/thin/vhdl/nodes.py index 2c2c00386..7a9b650c1 100644 --- a/python/libghdl/thin/vhdl/nodes.py +++ b/python/libghdl/thin/vhdl/nodes.py @@ -1365,96 +1365,98 @@ class Iir_Predefined: Ieee_Numeric_Std_Match_Sgn = 382 Ieee_Numeric_Std_Match_Slv = 383 Ieee_Numeric_Std_Match_Suv = 384 - Ieee_Math_Real_Ceil = 385 - Ieee_Math_Real_Round = 386 - Ieee_Math_Real_Log2 = 387 - Ieee_Math_Real_Sin = 388 - Ieee_Math_Real_Cos = 389 - Ieee_Std_Logic_Unsigned_Add_Slv_Slv = 390 - Ieee_Std_Logic_Unsigned_Add_Slv_Int = 391 - Ieee_Std_Logic_Unsigned_Add_Int_Slv = 392 - Ieee_Std_Logic_Unsigned_Add_Slv_Log = 393 - Ieee_Std_Logic_Unsigned_Add_Log_Slv = 394 - Ieee_Std_Logic_Unsigned_Sub_Slv_Slv = 395 - Ieee_Std_Logic_Unsigned_Sub_Slv_Int = 396 - Ieee_Std_Logic_Unsigned_Sub_Int_Slv = 397 - Ieee_Std_Logic_Unsigned_Sub_Slv_Log = 398 - Ieee_Std_Logic_Unsigned_Sub_Log_Slv = 399 - Ieee_Std_Logic_Unsigned_Mul_Slv_Slv = 400 - Ieee_Std_Logic_Unsigned_Lt_Slv_Slv = 401 - Ieee_Std_Logic_Unsigned_Lt_Slv_Int = 402 - Ieee_Std_Logic_Unsigned_Lt_Int_Slv = 403 - Ieee_Std_Logic_Unsigned_Le_Slv_Slv = 404 - Ieee_Std_Logic_Unsigned_Le_Slv_Int = 405 - Ieee_Std_Logic_Unsigned_Le_Int_Slv = 406 - Ieee_Std_Logic_Unsigned_Gt_Slv_Slv = 407 - Ieee_Std_Logic_Unsigned_Gt_Slv_Int = 408 - Ieee_Std_Logic_Unsigned_Gt_Int_Slv = 409 - Ieee_Std_Logic_Unsigned_Ge_Slv_Slv = 410 - Ieee_Std_Logic_Unsigned_Ge_Slv_Int = 411 - Ieee_Std_Logic_Unsigned_Ge_Int_Slv = 412 - Ieee_Std_Logic_Unsigned_Eq_Slv_Slv = 413 - Ieee_Std_Logic_Unsigned_Eq_Slv_Int = 414 - Ieee_Std_Logic_Unsigned_Eq_Int_Slv = 415 - Ieee_Std_Logic_Unsigned_Ne_Slv_Slv = 416 - Ieee_Std_Logic_Unsigned_Ne_Slv_Int = 417 - Ieee_Std_Logic_Unsigned_Ne_Int_Slv = 418 - Ieee_Std_Logic_Unsigned_Conv_Integer = 419 - Ieee_Std_Logic_Signed_Add_Slv_Slv = 420 - Ieee_Std_Logic_Signed_Add_Slv_Int = 421 - Ieee_Std_Logic_Signed_Add_Int_Slv = 422 - Ieee_Std_Logic_Signed_Add_Slv_Log = 423 - Ieee_Std_Logic_Signed_Add_Log_Slv = 424 - Ieee_Std_Logic_Signed_Sub_Slv_Slv = 425 - Ieee_Std_Logic_Signed_Sub_Slv_Int = 426 - Ieee_Std_Logic_Signed_Sub_Int_Slv = 427 - Ieee_Std_Logic_Signed_Sub_Slv_Log = 428 - Ieee_Std_Logic_Signed_Sub_Log_Slv = 429 - Ieee_Std_Logic_Signed_Mul_Slv_Slv = 430 - Ieee_Std_Logic_Arith_Conv_Unsigned_Int = 431 - Ieee_Std_Logic_Arith_Conv_Unsigned_Uns = 432 - Ieee_Std_Logic_Arith_Conv_Unsigned_Sgn = 433 - Ieee_Std_Logic_Arith_Conv_Unsigned_Log = 434 - Ieee_Std_Logic_Arith_Conv_Integer_Int = 435 - Ieee_Std_Logic_Arith_Conv_Integer_Uns = 436 - Ieee_Std_Logic_Arith_Conv_Integer_Sgn = 437 - Ieee_Std_Logic_Arith_Conv_Integer_Log = 438 - Ieee_Std_Logic_Arith_Conv_Vector_Int = 439 - Ieee_Std_Logic_Arith_Conv_Vector_Uns = 440 - Ieee_Std_Logic_Arith_Conv_Vector_Sgn = 441 - Ieee_Std_Logic_Arith_Conv_Vector_Log = 442 - Ieee_Std_Logic_Arith_Mul_Uns_Uns_Uns = 443 - Ieee_Std_Logic_Arith_Mul_Sgn_Sgn_Sgn = 444 - Ieee_Std_Logic_Arith_Mul_Sgn_Uns_Sgn = 445 - Ieee_Std_Logic_Arith_Mul_Uns_Sgn_Sgn = 446 - Ieee_Std_Logic_Arith_Mul_Uns_Uns_Slv = 447 - Ieee_Std_Logic_Arith_Mul_Sgn_Sgn_Slv = 448 - Ieee_Std_Logic_Arith_Mul_Sgn_Uns_Slv = 449 - Ieee_Std_Logic_Arith_Mul_Uns_Sgn_Slv = 450 - Ieee_Std_Logic_Arith_Add_Uns_Uns_Uns = 451 - Ieee_Std_Logic_Arith_Add_Sgn_Sgn_Sgn = 452 - Ieee_Std_Logic_Arith_Add_Uns_Sgn_Sgn = 453 - Ieee_Std_Logic_Arith_Add_Sgn_Uns_Sgn = 454 - Ieee_Std_Logic_Arith_Add_Uns_Int_Uns = 455 - Ieee_Std_Logic_Arith_Add_Int_Uns_Uns = 456 - Ieee_Std_Logic_Arith_Add_Sgn_Int_Sgn = 457 - Ieee_Std_Logic_Arith_Add_Int_Sgn_Sgn = 458 - Ieee_Std_Logic_Arith_Add_Uns_Log_Uns = 459 - Ieee_Std_Logic_Arith_Add_Log_Uns_Uns = 460 - Ieee_Std_Logic_Arith_Add_Sgn_Log_Sgn = 461 - Ieee_Std_Logic_Arith_Add_Log_Sgn_Sgn = 462 - Ieee_Std_Logic_Arith_Add_Uns_Uns_Slv = 463 - Ieee_Std_Logic_Arith_Add_Sgn_Sgn_Slv = 464 - Ieee_Std_Logic_Arith_Add_Uns_Sgn_Slv = 465 - Ieee_Std_Logic_Arith_Add_Sgn_Uns_Slv = 466 - Ieee_Std_Logic_Arith_Add_Uns_Int_Slv = 467 - Ieee_Std_Logic_Arith_Add_Int_Uns_Slv = 468 - Ieee_Std_Logic_Arith_Add_Sgn_Int_Slv = 469 - Ieee_Std_Logic_Arith_Add_Int_Sgn_Slv = 470 - Ieee_Std_Logic_Arith_Add_Uns_Log_Slv = 471 - Ieee_Std_Logic_Arith_Add_Log_Uns_Slv = 472 - Ieee_Std_Logic_Arith_Add_Sgn_Log_Slv = 473 - Ieee_Std_Logic_Arith_Add_Log_Sgn_Slv = 474 + Ieee_Numeric_Std_To_01_Uns = 385 + Ieee_Numeric_Std_To_01_Sgn = 386 + Ieee_Math_Real_Ceil = 387 + Ieee_Math_Real_Round = 388 + Ieee_Math_Real_Log2 = 389 + Ieee_Math_Real_Sin = 390 + Ieee_Math_Real_Cos = 391 + Ieee_Std_Logic_Unsigned_Add_Slv_Slv = 392 + Ieee_Std_Logic_Unsigned_Add_Slv_Int = 393 + Ieee_Std_Logic_Unsigned_Add_Int_Slv = 394 + Ieee_Std_Logic_Unsigned_Add_Slv_Log = 395 + Ieee_Std_Logic_Unsigned_Add_Log_Slv = 396 + Ieee_Std_Logic_Unsigned_Sub_Slv_Slv = 397 + Ieee_Std_Logic_Unsigned_Sub_Slv_Int = 398 + Ieee_Std_Logic_Unsigned_Sub_Int_Slv = 399 + Ieee_Std_Logic_Unsigned_Sub_Slv_Log = 400 + Ieee_Std_Logic_Unsigned_Sub_Log_Slv = 401 + Ieee_Std_Logic_Unsigned_Mul_Slv_Slv = 402 + Ieee_Std_Logic_Unsigned_Lt_Slv_Slv = 403 + Ieee_Std_Logic_Unsigned_Lt_Slv_Int = 404 + Ieee_Std_Logic_Unsigned_Lt_Int_Slv = 405 + Ieee_Std_Logic_Unsigned_Le_Slv_Slv = 406 + Ieee_Std_Logic_Unsigned_Le_Slv_Int = 407 + Ieee_Std_Logic_Unsigned_Le_Int_Slv = 408 + Ieee_Std_Logic_Unsigned_Gt_Slv_Slv = 409 + Ieee_Std_Logic_Unsigned_Gt_Slv_Int = 410 + Ieee_Std_Logic_Unsigned_Gt_Int_Slv = 411 + Ieee_Std_Logic_Unsigned_Ge_Slv_Slv = 412 + Ieee_Std_Logic_Unsigned_Ge_Slv_Int = 413 + Ieee_Std_Logic_Unsigned_Ge_Int_Slv = 414 + Ieee_Std_Logic_Unsigned_Eq_Slv_Slv = 415 + Ieee_Std_Logic_Unsigned_Eq_Slv_Int = 416 + Ieee_Std_Logic_Unsigned_Eq_Int_Slv = 417 + Ieee_Std_Logic_Unsigned_Ne_Slv_Slv = 418 + Ieee_Std_Logic_Unsigned_Ne_Slv_Int = 419 + Ieee_Std_Logic_Unsigned_Ne_Int_Slv = 420 + Ieee_Std_Logic_Unsigned_Conv_Integer = 421 + Ieee_Std_Logic_Signed_Add_Slv_Slv = 422 + Ieee_Std_Logic_Signed_Add_Slv_Int = 423 + Ieee_Std_Logic_Signed_Add_Int_Slv = 424 + Ieee_Std_Logic_Signed_Add_Slv_Log = 425 + Ieee_Std_Logic_Signed_Add_Log_Slv = 426 + Ieee_Std_Logic_Signed_Sub_Slv_Slv = 427 + Ieee_Std_Logic_Signed_Sub_Slv_Int = 428 + Ieee_Std_Logic_Signed_Sub_Int_Slv = 429 + Ieee_Std_Logic_Signed_Sub_Slv_Log = 430 + Ieee_Std_Logic_Signed_Sub_Log_Slv = 431 + Ieee_Std_Logic_Signed_Mul_Slv_Slv = 432 + Ieee_Std_Logic_Arith_Conv_Unsigned_Int = 433 + Ieee_Std_Logic_Arith_Conv_Unsigned_Uns = 434 + Ieee_Std_Logic_Arith_Conv_Unsigned_Sgn = 435 + Ieee_Std_Logic_Arith_Conv_Unsigned_Log = 436 + Ieee_Std_Logic_Arith_Conv_Integer_Int = 437 + Ieee_Std_Logic_Arith_Conv_Integer_Uns = 438 + Ieee_Std_Logic_Arith_Conv_Integer_Sgn = 439 + Ieee_Std_Logic_Arith_Conv_Integer_Log = 440 + Ieee_Std_Logic_Arith_Conv_Vector_Int = 441 + Ieee_Std_Logic_Arith_Conv_Vector_Uns = 442 + Ieee_Std_Logic_Arith_Conv_Vector_Sgn = 443 + Ieee_Std_Logic_Arith_Conv_Vector_Log = 444 + Ieee_Std_Logic_Arith_Mul_Uns_Uns_Uns = 445 + Ieee_Std_Logic_Arith_Mul_Sgn_Sgn_Sgn = 446 + Ieee_Std_Logic_Arith_Mul_Sgn_Uns_Sgn = 447 + Ieee_Std_Logic_Arith_Mul_Uns_Sgn_Sgn = 448 + Ieee_Std_Logic_Arith_Mul_Uns_Uns_Slv = 449 + Ieee_Std_Logic_Arith_Mul_Sgn_Sgn_Slv = 450 + Ieee_Std_Logic_Arith_Mul_Sgn_Uns_Slv = 451 + Ieee_Std_Logic_Arith_Mul_Uns_Sgn_Slv = 452 + Ieee_Std_Logic_Arith_Add_Uns_Uns_Uns = 453 + Ieee_Std_Logic_Arith_Add_Sgn_Sgn_Sgn = 454 + Ieee_Std_Logic_Arith_Add_Uns_Sgn_Sgn = 455 + Ieee_Std_Logic_Arith_Add_Sgn_Uns_Sgn = 456 + Ieee_Std_Logic_Arith_Add_Uns_Int_Uns = 457 + Ieee_Std_Logic_Arith_Add_Int_Uns_Uns = 458 + Ieee_Std_Logic_Arith_Add_Sgn_Int_Sgn = 459 + Ieee_Std_Logic_Arith_Add_Int_Sgn_Sgn = 460 + Ieee_Std_Logic_Arith_Add_Uns_Log_Uns = 461 + Ieee_Std_Logic_Arith_Add_Log_Uns_Uns = 462 + Ieee_Std_Logic_Arith_Add_Sgn_Log_Sgn = 463 + Ieee_Std_Logic_Arith_Add_Log_Sgn_Sgn = 464 + Ieee_Std_Logic_Arith_Add_Uns_Uns_Slv = 465 + Ieee_Std_Logic_Arith_Add_Sgn_Sgn_Slv = 466 + Ieee_Std_Logic_Arith_Add_Uns_Sgn_Slv = 467 + Ieee_Std_Logic_Arith_Add_Sgn_Uns_Slv = 468 + Ieee_Std_Logic_Arith_Add_Uns_Int_Slv = 469 + Ieee_Std_Logic_Arith_Add_Int_Uns_Slv = 470 + Ieee_Std_Logic_Arith_Add_Sgn_Int_Slv = 471 + Ieee_Std_Logic_Arith_Add_Int_Sgn_Slv = 472 + Ieee_Std_Logic_Arith_Add_Uns_Log_Slv = 473 + Ieee_Std_Logic_Arith_Add_Log_Uns_Slv = 474 + Ieee_Std_Logic_Arith_Add_Sgn_Log_Slv = 475 + Ieee_Std_Logic_Arith_Add_Log_Sgn_Slv = 476 Get_Kind = libghdl.vhdl__nodes__get_kind Get_Location = libghdl.vhdl__nodes__get_location diff --git a/src/std_names.adb b/src/std_names.adb index 303d14eed..9d9cfcbe7 100644 --- a/src/std_names.adb +++ b/src/std_names.adb @@ -652,6 +652,7 @@ package body Std_Names is Def ("to_stdlogicvector", Name_To_Stdlogicvector); Def ("to_stdulogicvector", Name_To_Stdulogicvector); Def ("is_x", Name_Is_X); + Def ("to_01", Name_To_01); Def ("conv_signed", Name_Conv_Signed); Def ("conv_unsigned", Name_Conv_Unsigned); Def ("conv_integer", Name_Conv_Integer); @@ -786,6 +787,8 @@ package body Std_Names is Def ("synopsys", Name_Synopsys); Def ("translate_off", Name_Translate_Off); Def ("translate_on", Name_Translate_On); + Def ("translate", Name_Translate); + Def ("off", Name_Off); -- PSL keywords Def ("a", Name_A); diff --git a/src/std_names.ads b/src/std_names.ads index 6363db8b8..2c12c0f00 100644 --- a/src/std_names.ads +++ b/src/std_names.ads @@ -735,21 +735,22 @@ package Std_Names is Name_To_Stdlogicvector : constant Name_Id := Name_First_Ieee_Name + 022; Name_To_Stdulogicvector : constant Name_Id := Name_First_Ieee_Name + 023; Name_Is_X : constant Name_Id := Name_First_Ieee_Name + 024; - Name_Conv_Signed : constant Name_Id := Name_First_Ieee_Name + 025; - Name_Conv_Unsigned : constant Name_Id := Name_First_Ieee_Name + 026; - Name_Conv_Integer : constant Name_Id := Name_First_Ieee_Name + 027; - Name_Conv_Std_Logic_Vector : constant Name_Id := Name_First_Ieee_Name + 028; - Name_And_Reduce : constant Name_Id := Name_First_Ieee_Name + 029; - Name_Nand_Reduce : constant Name_Id := Name_First_Ieee_Name + 030; - Name_Or_Reduce : constant Name_Id := Name_First_Ieee_Name + 031; - Name_Nor_Reduce : constant Name_Id := Name_First_Ieee_Name + 032; - Name_Xor_Reduce : constant Name_Id := Name_First_Ieee_Name + 033; - Name_Xnor_Reduce : constant Name_Id := Name_First_Ieee_Name + 034; - Name_Ceil : constant Name_Id := Name_First_Ieee_Name + 035; - Name_Round : constant Name_Id := Name_First_Ieee_Name + 036; - Name_Log2 : constant Name_Id := Name_First_Ieee_Name + 037; - Name_Sin : constant Name_Id := Name_First_Ieee_Name + 038; - Name_Cos : constant Name_Id := Name_First_Ieee_Name + 039; + Name_To_01 : constant Name_Id := Name_First_Ieee_Name + 025; + Name_Conv_Signed : constant Name_Id := Name_First_Ieee_Name + 026; + Name_Conv_Unsigned : constant Name_Id := Name_First_Ieee_Name + 027; + Name_Conv_Integer : constant Name_Id := Name_First_Ieee_Name + 028; + Name_Conv_Std_Logic_Vector : constant Name_Id := Name_First_Ieee_Name + 029; + Name_And_Reduce : constant Name_Id := Name_First_Ieee_Name + 030; + Name_Nand_Reduce : constant Name_Id := Name_First_Ieee_Name + 031; + Name_Or_Reduce : constant Name_Id := Name_First_Ieee_Name + 032; + Name_Nor_Reduce : constant Name_Id := Name_First_Ieee_Name + 033; + Name_Xor_Reduce : constant Name_Id := Name_First_Ieee_Name + 034; + Name_Xnor_Reduce : constant Name_Id := Name_First_Ieee_Name + 035; + Name_Ceil : constant Name_Id := Name_First_Ieee_Name + 036; + Name_Round : constant Name_Id := Name_First_Ieee_Name + 037; + Name_Log2 : constant Name_Id := Name_First_Ieee_Name + 038; + Name_Sin : constant Name_Id := Name_First_Ieee_Name + 039; + Name_Cos : constant Name_Id := Name_First_Ieee_Name + 040; Name_Last_Ieee_Name : constant Name_Id := Name_Cos; Name_First_Synthesis : constant Name_Id := Name_Last_Ieee_Name + 1; @@ -915,7 +916,9 @@ package Std_Names is Name_Synopsys : constant Name_Id := Name_First_Comment + 3; Name_Translate_Off : constant Name_Id := Name_First_Comment + 4; Name_Translate_On : constant Name_Id := Name_First_Comment + 5; - Name_Last_Comment : constant Name_Id := Name_Translate_On; + Name_Translate : constant Name_Id := Name_First_Comment + 6; + Name_Off : constant Name_Id := Name_First_Comment + 7; + Name_Last_Comment : constant Name_Id := Name_Off; -- PSL words. Name_First_PSL : constant Name_Id := Name_Last_Comment + 1; diff --git a/src/synth/synth-oper.adb b/src/synth/synth-oper.adb index 8efaca0c3..ed962e378 100644 --- a/src/synth/synth-oper.adb +++ b/src/synth/synth-oper.adb @@ -1481,13 +1481,11 @@ package body Synth.Oper is | Iir_Predefined_Ieee_1164_Vector_Is_X => -- Always false. return Create_Value_Discrete (0, Boolean_Type); - when Iir_Predefined_Ieee_1164_To_Bitvector => - if Is_Static (L) then - raise Internal_Error; - end if; - return Create_Value_Net (Get_Net (L), Create_Res_Bound (L)); - when Iir_Predefined_Ieee_1164_To_Stdlogicvector_Suv - | Iir_Predefined_Ieee_1164_To_Stdlogicvector_Bv => + when Iir_Predefined_Ieee_1164_To_Bitvector + | Iir_Predefined_Ieee_1164_To_Stdlogicvector_Suv + | Iir_Predefined_Ieee_1164_To_Stdlogicvector_Bv + | Iir_Predefined_Ieee_Numeric_Std_To_01_Uns + | Iir_Predefined_Ieee_Numeric_Std_To_01_Sgn => if Is_Static (L) then raise Internal_Error; end if; diff --git a/src/vhdl/vhdl-ieee-numeric.adb b/src/vhdl/vhdl-ieee-numeric.adb index 8f94b8fde..7be77ac8f 100644 --- a/src/vhdl/vhdl-ieee-numeric.adb +++ b/src/vhdl/vhdl-ieee-numeric.adb @@ -718,6 +718,29 @@ package body Vhdl.Ieee.Numeric is Set_Implicit_Definition (Decl, Predefined); end Handle_Std_Match; + procedure Handle_To_01 + is + Predefined : Iir_Predefined_Functions; + begin + if Arg1_Kind /= Arg_Vect + or else Arg2_Kind /= Arg_Scal + or else Arg2_Sign /= Type_Log + then + raise Error; + end if; + + case Arg1_Sign is + when Type_Unsigned => + Predefined := Iir_Predefined_Ieee_Numeric_Std_To_01_Uns; + when Type_Signed => + Predefined := Iir_Predefined_Ieee_Numeric_Std_To_01_Sgn; + when others => + raise Error; + end case; + + Set_Implicit_Definition (Decl, Predefined); + end Handle_To_01; + procedure Handle_Shift (Pats : Shift_Pattern_Type; Sh_Sign : Sign_Kind) is Res : Iir_Predefined_Functions; @@ -885,6 +908,8 @@ package body Vhdl.Ieee.Numeric is Handle_Shift (Rol_Patterns, Type_Unsigned); when Name_Rotate_Right => Handle_Shift (Ror_Patterns, Type_Unsigned); + when Name_To_01 => + Handle_To_01; when others => null; end case; diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index 7c2bebd42..d27e1aed9 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -5692,6 +5692,9 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_Numeric_Std_Match_Slv, Iir_Predefined_Ieee_Numeric_Std_Match_Suv, + Iir_Predefined_Ieee_Numeric_Std_To_01_Uns, + Iir_Predefined_Ieee_Numeric_Std_To_01_Sgn, + -- Math_Real Iir_Predefined_Ieee_Math_Real_Ceil, Iir_Predefined_Ieee_Math_Real_Round, |