elab-vhdl_objtypes: use value_offsets for record elements offset.

12 files changed, 52 insertions, 56 deletions

diff --git a/src/synth/elab-vhdl_expr.adb b/src/synth/elab-vhdl_expr.adb
index 61d47cdfc..488a2984f 100644
--- a/src/synth/elab-vhdl_expr.adb
+++ b/src/synth/elab-vhdl_expr.adb
@@ -771,10 +771,7 @@ package body Elab.Vhdl_Expr is
             begin
                Exec_Assignment_Prefix
                  (Syn_Inst, Get_Prefix (Pfx), Dest_Base, Dest_Typ, Dest_Off);
-               Dest_Off.Net_Off :=
-                 Dest_Off.Net_Off + Dest_Typ.Rec.E (Idx + 1).Boff;
-               Dest_Off.Mem_Off :=
-                 Dest_Off.Mem_Off + Dest_Typ.Rec.E (Idx + 1).Moff;
+               Dest_Off := Dest_Off + Dest_Typ.Rec.E (Idx + 1).Offs;
 
                Dest_Typ := Dest_Typ.Rec.E (Idx + 1).Typ;
             end;
@@ -1188,7 +1185,8 @@ package body Elab.Vhdl_Expr is
                pragma Assert (Is_Static (Val.Val));
                Res := Create_Value_Memory (Res_Typ);
                Copy_Memory
-                 (Res.Val.Mem, Val.Val.Mem + Val.Typ.Rec.E (Idx + 1).Moff,
+                 (Res.Val.Mem,
+                  Val.Val.Mem + Val.Typ.Rec.E (Idx + 1).Offs.Mem_Off,
                   Res_Typ.Sz);
                return Res;
             end;
diff --git a/src/synth/elab-vhdl_files.adb b/src/synth/elab-vhdl_files.adb
index c974a835d..12afedd91 100644
--- a/src/synth/elab-vhdl_files.adb
+++ b/src/synth/elab-vhdl_files.adb
@@ -455,8 +455,8 @@ package body Elab.Vhdl_Files is
          when Type_Record =>
             for I in Val.Typ.Rec.E'Range loop
                File_Read_Value
-                 (File,
-                  (Val.Typ.Rec.E (I).Typ, Val.Mem + Val.Typ.Rec.E (I).Moff),
+                 (File, (Val.Typ.Rec.E (I).Typ,
+                         Val.Mem + Val.Typ.Rec.E (I).Offs.Mem_Off),
                   Loc);
             end loop;
          when Type_Unbounded_Record
@@ -509,10 +509,10 @@ package body Elab.Vhdl_Files is
             end;
          when Type_Record =>
             for I in Val.Typ.Rec.E'Range loop
-               File_Write_Value
-                 (File,
-                  (Val.Typ.Rec.E (I).Typ, Val.Mem + Val.Typ.Rec.E (I).Moff),
-                  Loc);
+               File_Write_Value (File,
+                                 (Val.Typ.Rec.E (I).Typ,
+                                  Val.Mem + Val.Typ.Rec.E (I).Offs.Mem_Off),
+                                 Loc);
             end loop;
          when Type_Unbounded_Record
             | Type_Unbounded_Array
diff --git a/src/synth/elab-vhdl_objtypes.adb b/src/synth/elab-vhdl_objtypes.adb
index cc13cf2a3..782f4dfa6 100644
--- a/src/synth/elab-vhdl_objtypes.adb
+++ b/src/synth/elab-vhdl_objtypes.adb
@@ -482,7 +482,7 @@ package body Elab.Vhdl_Objtypes is
             E : Rec_El_Type renames Els.E (I);
          begin
             --  For nets.
-            E.Boff := W;
+            E.Offs.Net_Off := W;
             if E.Typ.Wkind /= Wkind_Net then
                Wkind := Wkind_Undef;
             end if;
@@ -491,7 +491,7 @@ package body Elab.Vhdl_Objtypes is
             --  For memory.
             Al := Palign_Type'Max (Al, E.Typ.Al);
             Sz := Align (Sz, E.Typ.Al);
-            E.Moff := Sz;
+            E.Offs.Mem_Off := Sz;
             Sz := Sz + E.Typ.Sz;
          end;
       end loop;
diff --git a/src/synth/elab-vhdl_objtypes.ads b/src/synth/elab-vhdl_objtypes.ads
index 9969d9cb8..850f268b4 100644
--- a/src/synth/elab-vhdl_objtypes.ads
+++ b/src/synth/elab-vhdl_objtypes.ads
@@ -56,6 +56,16 @@ package Elab.Vhdl_Objtypes is
       Len : Uns32;
    end record;
 
+   --  Offsets for a value.
+   type Value_Offsets is record
+      Net_Off : Uns32;
+      Mem_Off : Size_Type;
+   end record;
+
+   No_Value_Offsets : constant Value_Offsets := (0, 0);
+
+   function "+" (L, R : Value_Offsets) return Value_Offsets;
+
    type Type_Kind is
      (
       Type_Bit,
@@ -87,11 +97,8 @@ package Elab.Vhdl_Objtypes is
    type Type_Acc is access Type_Type;
 
    type Rec_El_Type is record
-      --  Bit offset: offset of the element in a net.
-      Boff : Uns32;
-
-      --  Memory offset: offset of the element in memory.
-      Moff : Size_Type;
+      --  Offset of the element.
+      Offs : Value_Offsets;
 
       --  Type of the element.
       Typ : Type_Acc;
@@ -179,16 +186,6 @@ package Elab.Vhdl_Objtypes is
 
    Null_Memtyp : constant Memtyp := (null, null);
 
-   --  Offsets for a value.
-   type Value_Offsets is record
-      Net_Off : Uns32;
-      Mem_Off : Size_Type;
-   end record;
-
-   No_Value_Offsets : constant Value_Offsets := (0, 0);
-
-   function "+" (L, R : Value_Offsets) return Value_Offsets;
-
    Global_Pool : aliased Areapool;
    Expr_Pool : aliased Areapool;
 
diff --git a/src/synth/elab-vhdl_values-debug.adb b/src/synth/elab-vhdl_values-debug.adb
index 227764734..60d29dc1a 100644
--- a/src/synth/elab-vhdl_values-debug.adb
+++ b/src/synth/elab-vhdl_values-debug.adb
@@ -98,10 +98,10 @@ package body Elab.Vhdl_Values.Debug is
                if I /= 1 then
                   Put (", ");
                end if;
-               Put ("[boff=");
-               Put_Uns32 (T.Rec.E (I).Boff);
+               Put ("[noff=");
+               Put_Uns32 (T.Rec.E (I).Offs.Net_Off);
                Put (", moff=");
-               Put_Uns32 (Uns32 (T.Rec.E (I).Moff));
+               Put_Uns32 (Uns32 (T.Rec.E (I).Offs.Mem_Off));
                Put ("] ");
                Debug_Typ1 (T.Rec.E (I).Typ);
             end loop;
@@ -254,7 +254,7 @@ package body Elab.Vhdl_Values.Debug is
                   Put (", ");
                end if;
                Debug_Memtyp
-                 ((M.Typ.Rec.E (I).Typ, M.Mem + M.Typ.Rec.E (I).Moff));
+                 ((M.Typ.Rec.E (I).Typ, M.Mem + M.Typ.Rec.E (I).Offs.Mem_Off));
             end loop;
             Put (")");
          when Type_Discrete =>
diff --git a/src/synth/elab-vhdl_values.adb b/src/synth/elab-vhdl_values.adb
index 3187671db..03f70943f 100644
--- a/src/synth/elab-vhdl_values.adb
+++ b/src/synth/elab-vhdl_values.adb
@@ -389,7 +389,8 @@ package body Elab.Vhdl_Values is
             raise Internal_Error;
          when Type_Record =>
             for I in Typ.Rec.E'Range loop
-               Write_Value_Default (M + Typ.Rec.E (I).Moff, Typ.Rec.E (I).Typ);
+               Write_Value_Default (M + Typ.Rec.E (I).Offs.Mem_Off,
+                                    Typ.Rec.E (I).Typ);
             end loop;
          when Type_Access =>
             Write_Access (M, Null_Heap_Index);
diff --git a/src/synth/synth-disp_vhdl.adb b/src/synth/synth-disp_vhdl.adb
index 8243a89ff..f7ef56c50 100644
--- a/src/synth/synth-disp_vhdl.adb
+++ b/src/synth/synth-disp_vhdl.adb
@@ -230,7 +230,8 @@ package body Synth.Disp_Vhdl is
                      Disp_In_Converter
                        (Mname,
                         Pfx & '.' & Name_Table.Image (Get_Identifier (El)),
-                        Off + Et.Boff, Get_Type (El), Et.Typ, Rec_Full);
+                        Off + Et.Offs.Net_Off,
+                        Get_Type (El), Et.Typ, Rec_Full);
                   end;
                end loop;
             end;
@@ -409,7 +410,8 @@ package body Synth.Disp_Vhdl is
                      Disp_Out_Converter
                        (Mname,
                         Pfx & '.' & Name_Table.Image (Get_Identifier (El)),
-                        Off + Et.Boff, Get_Type (El), Et.Typ, Rec_Full);
+                        Off + Et.Offs.Net_Off,
+                        Get_Type (El), Et.Typ, Rec_Full);
                   end;
                end loop;
             end;
diff --git a/src/synth/synth-vhdl_aggr.adb b/src/synth/synth-vhdl_aggr.adb
index 380d8d391..bb355726e 100644
--- a/src/synth/synth-vhdl_aggr.adb
+++ b/src/synth/synth-vhdl_aggr.adb
@@ -515,7 +515,7 @@ package body Synth.Vhdl_Aggr is
             for I in Aggr_Type.Rec.E'Range loop
                --  Note: elements are put in reverse order in Tab_Res,
                --  so reverse again...
-               Write_Value (Res.Val.Mem + Res_Typ.Rec.E (I).Moff,
+               Write_Value (Res.Val.Mem + Res_Typ.Rec.E (I).Offs.Mem_Off,
                             Tab_Res (Tab_Res'Last - Nat32 (I) + 1));
             end loop;
          else
diff --git a/src/synth/synth-vhdl_environment.adb b/src/synth/synth-vhdl_environment.adb
index 711673fda..e86cd7a7c 100644
--- a/src/synth/synth-vhdl_environment.adb
+++ b/src/synth/synth-vhdl_environment.adb
@@ -142,14 +142,14 @@ package body Synth.Vhdl_Environment is
                      Sub_Off : Uns32;
                      Sub_Wd : Width;
                   begin
-                     if Off + Wd <= El.Boff then
+                     if Off + Wd <= El.Offs.Net_Off then
                         --  Not covered anymore.
                         exit;
-                     elsif Off >= El.Boff + El.Typ.W then
+                     elsif Off >= El.Offs.Net_Off + El.Typ.W then
                         --  Not yet covered.
                         null;
-                     elsif Off <= El.Boff
-                       and then Off + Wd >= El.Boff + El.Typ.W
+                     elsif Off <= El.Offs.Net_Off
+                       and then Off + Wd >= El.Offs.Net_Off + El.Typ.W
                      then
                         --  Fully covered.
                         Info_Msg_Synth
@@ -158,13 +158,13 @@ package body Synth.Vhdl_Environment is
                              & Vhdl.Utils.Image_Identifier (Field));
                      else
                         --  Partially covered.
-                        if Off < El.Boff then
+                        if Off < El.Offs.Net_Off then
                            Sub_Off := 0;
-                           Sub_Wd := Wd - (El.Boff - Off);
+                           Sub_Wd := Wd - (El.Offs.Net_Off - Off);
                            Sub_Wd := Width'Min (Sub_Wd, El.Typ.W);
                         else
-                           Sub_Off := Off - El.Boff;
-                           Sub_Wd := El.Typ.W - (Off - El.Boff);
+                           Sub_Off := Off - El.Offs.Net_Off;
+                           Sub_Wd := El.Typ.W - (Off - El.Offs.Net_Off);
                            Sub_Wd := Width'Min (Sub_Wd, Wd);
                         end if;
                         Info_Subnet_Vhdl
diff --git a/src/synth/synth-vhdl_expr.adb b/src/synth/synth-vhdl_expr.adb
index fe1fb0cbe..6ec6e5e12 100644
--- a/src/synth/synth-vhdl_expr.adb
+++ b/src/synth/synth-vhdl_expr.adb
@@ -350,8 +350,8 @@ package body Synth.Vhdl_Expr is
             end;
          when Type_Record =>
             for I in Typ.Rec.E'Range loop
-               Value2logvec (Mem + Typ.Rec.E (I).Moff, Typ.Rec.E (I).Typ,
-                             Off, W, Vec, Vec_Off, Has_Zx);
+               Value2logvec (Mem + Typ.Rec.E (I).Offs.Mem_Off,
+                             Typ.Rec.E (I).Typ, Off, W, Vec, Vec_Off, Has_Zx);
                exit when W = 0;
             end loop;
          when Type_Access =>
@@ -2009,13 +2009,14 @@ package body Synth.Vhdl_Expr is
                elsif Is_Static (Val.Val) then
                   Res := Create_Value_Memory (Res_Typ);
                   Copy_Memory
-                    (Res.Val.Mem, Val.Val.Mem + Val.Typ.Rec.E (Idx + 1).Moff,
+                    (Res.Val.Mem,
+                     Val.Val.Mem + Val.Typ.Rec.E (Idx + 1).Offs.Mem_Off,
                      Res_Typ.Sz);
                   return Res;
                else
-                  N := Build_Extract
-                    (Ctxt, Get_Net (Ctxt, Val),
-                     Val.Typ.Rec.E (Idx + 1).Boff, Get_Type_Width (Res_Typ));
+                  N := Build_Extract (Ctxt, Get_Net (Ctxt, Val),
+                                      Val.Typ.Rec.E (Idx + 1).Offs.Net_Off,
+                                      Get_Type_Width (Res_Typ));
                   Set_Location (N, Expr);
                   return Create_Value_Net (N, Res_Typ);
                end if;
diff --git a/src/synth/synth-vhdl_insts.adb b/src/synth/synth-vhdl_insts.adb
index bf487ad0c..5e6b39669 100644
--- a/src/synth/synth-vhdl_insts.adb
+++ b/src/synth/synth-vhdl_insts.adb
@@ -650,7 +650,7 @@ package body Synth.Vhdl_Insts is
             begin
                Synth_Individual_Prefix
                  (Syn_Inst, Inter_Inst, Get_Prefix (Formal), Off, Typ);
-               Off := Off + Typ.Rec.E (Idx + 1).Boff;
+               Off := Off + Typ.Rec.E (Idx + 1).Offs.Net_Off;
                Typ := Typ.Rec.E (Idx + 1).Typ;
             end;
          when Iir_Kind_Indexed_Name =>
@@ -907,7 +907,7 @@ package body Synth.Vhdl_Insts is
                if N /= No_Net then
                   Connect (Get_Input (Inst, Port),
                            Build_Extract (Get_Build (Syn_Inst), N,
-                                          Inter_Typ.Rec.E (I).Boff,
+                                          Inter_Typ.Rec.E (I).Offs.Net_Off,
                                           Inter_Typ.Rec.E (I).Typ.W));
                end if;
                Port := Port + 1;
diff --git a/src/synth/synth-vhdl_stmts.adb b/src/synth/synth-vhdl_stmts.adb
index 2539fad87..02f6dd6b7 100644
--- a/src/synth/synth-vhdl_stmts.adb
+++ b/src/synth/synth-vhdl_stmts.adb
@@ -192,10 +192,7 @@ package body Synth.Vhdl_Stmts is
                Synth_Assignment_Prefix
                  (Syn_Inst, Get_Prefix (Pfx),
                   Dest_Base, Dest_Typ, Dest_Off, Dest_Dyn);
-               Dest_Off.Net_Off :=
-                 Dest_Off.Net_Off + Dest_Typ.Rec.E (Idx + 1).Boff;
-               Dest_Off.Mem_Off :=
-                 Dest_Off.Mem_Off + Dest_Typ.Rec.E (Idx + 1).Moff;
+               Dest_Off := Dest_Off + Dest_Typ.Rec.E (Idx + 1).Offs;
 
                Dest_Typ := Dest_Typ.Rec.E (Idx + 1).Typ;
             end;