elab: add default value to ports

4 files changed, 28 insertions, 13 deletions

diff --git a/src/synth/elab-vhdl_decls.adb b/src/synth/elab-vhdl_decls.adb
index 0beb5997a..08f64a575 100644
--- a/src/synth/elab-vhdl_decls.adb
+++ b/src/synth/elab-vhdl_decls.adb
@@ -19,7 +19,6 @@
 with Vhdl.Errors; use Vhdl.Errors;
 with Vhdl.Utils; use Vhdl.Utils;
 
-with Elab.Vhdl_Objtypes; use Elab.Vhdl_Objtypes;
 with Elab.Vhdl_Values; use Elab.Vhdl_Values;
 with Elab.Vhdl_Types; use Elab.Vhdl_Types;
 with Elab.Vhdl_Files;
@@ -104,22 +103,30 @@ package body Elab.Vhdl_Decls is
       Create_Object_Force (Syn_Inst, First_Decl, Val);
    end Elab_Constant_Declaration;
 
-   procedure Elab_Signal_Declaration (Syn_Inst : Synth_Instance_Acc;
-                                      Decl : Node)
+   procedure Create_Signal (Syn_Inst : Synth_Instance_Acc;
+                            Decl : Node;
+                            Typ : Type_Acc)
    is
       Def : constant Iir := Get_Default_Value (Decl);
       Init : Valtyp;
-      Obj_Typ : Type_Acc;
    begin
-      Obj_Typ := Elab_Declaration_Type (Syn_Inst, Decl);
-
       if Is_Valid (Def) then
-         Init := Synth_Expression_With_Type (Syn_Inst, Def, Obj_Typ);
-         Init := Exec_Subtype_Conversion (Init, Obj_Typ, False, Decl);
+         Init := Synth_Expression_With_Type (Syn_Inst, Def, Typ);
+         Init := Exec_Subtype_Conversion (Init, Typ, False, Decl);
       else
          Init := No_Valtyp;
       end if;
-      Create_Signal (Syn_Inst, Decl, Obj_Typ, Init.Val);
+      Create_Signal (Syn_Inst, Decl, Typ, Init.Val);
+   end Create_Signal;
+
+   procedure Elab_Signal_Declaration (Syn_Inst : Synth_Instance_Acc;
+                                      Decl : Node)
+   is
+      Obj_Typ : Type_Acc;
+   begin
+      Obj_Typ := Elab_Declaration_Type (Syn_Inst, Decl);
+
+      Create_Signal (Syn_Inst, Decl, Obj_Typ);
    end Elab_Signal_Declaration;
 
    procedure Elab_Variable_Declaration (Syn_Inst : Synth_Instance_Acc;
diff --git a/src/synth/elab-vhdl_decls.ads b/src/synth/elab-vhdl_decls.ads
index 8e45897b1..dd1d647d6 100644
--- a/src/synth/elab-vhdl_decls.ads
+++ b/src/synth/elab-vhdl_decls.ads
@@ -18,6 +18,7 @@
 
 with Vhdl.Nodes; use Vhdl.Nodes;
 
+with Elab.Vhdl_Objtypes; use Elab.Vhdl_Objtypes;
 with Elab.Vhdl_Context; use Elab.Vhdl_Context;
 
 package Elab.Vhdl_Decls is
@@ -40,4 +41,11 @@ package Elab.Vhdl_Decls is
                                     Decls : Iir;
                                     Is_Subprg : Boolean := False);
 
+   --  Create a signal.
+   --  It's a wrapper around elab.vhdl_context.create_signal but it computes
+   --  the default value.
+   --  Also used to create signals for ports.
+   procedure Create_Signal (Syn_Inst : Synth_Instance_Acc;
+                            Decl : Node;
+                            Typ : Type_Acc);
 end Elab.Vhdl_Decls;
diff --git a/src/synth/elab-vhdl_insts.adb b/src/synth/elab-vhdl_insts.adb
index 2a7babf27..045de2e1c 100644
--- a/src/synth/elab-vhdl_insts.adb
+++ b/src/synth/elab-vhdl_insts.adb
@@ -383,7 +383,7 @@ package body Elab.Vhdl_Insts is
          if Get_Whole_Association_Flag (Assoc) then
             Inter_Typ := Elab_Port_Association_Type
               (Sub_Inst, Syn_Inst, Inter, Assoc);
-            Create_Signal (Sub_Inst, Inter, Inter_Typ, null);
+            Create_Signal (Sub_Inst, Inter, Inter_Typ);
          end if;
          Next_Association_Interface (Assoc, Assoc_Inter);
       end loop;
@@ -673,7 +673,7 @@ package body Elab.Vhdl_Insts is
 
                Inter_Typ := Elab_Port_Association_Type
                  (Comp_Inst, Syn_Inst, Inter, Assoc);
-               Create_Signal (Comp_Inst, Inter, Inter_Typ, null);
+               Create_Signal (Comp_Inst, Inter, Inter_Typ);
             end if;
             Next_Association_Interface (Assoc, Assoc_Inter);
          end loop;
@@ -828,7 +828,7 @@ package body Elab.Vhdl_Insts is
             Inter_Typ : Type_Acc;
          begin
             Inter_Typ := Elab_Declaration_Type (Top_Inst, Inter);
-            Create_Signal (Top_Inst, Inter, Inter_Typ, null);
+            Create_Signal (Top_Inst, Inter, Inter_Typ);
          end;
          Inter := Get_Chain (Inter);
       end loop;
diff --git a/src/synth/elab-vhdl_objtypes.adb b/src/synth/elab-vhdl_objtypes.adb
index 6e4f9c1e3..87850f85a 100644
--- a/src/synth/elab-vhdl_objtypes.adb
+++ b/src/synth/elab-vhdl_objtypes.adb
@@ -302,7 +302,7 @@ package body Elab.Vhdl_Objtypes is
       pragma Assert (El_Type.Kind in Type_Nets);
       return To_Type_Acc
         (Alloc (Current_Pool, (Kind => Type_Vector,
-                               Wkind => Wkind_Net,
+                               Wkind => El_Type.Wkind,
                                Al => El_Type.Al,
                                Sz => El_Type.Sz * Size_Type (Bnd.Len),
                                W => Bnd.Len,