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| author | Christos Gentsos <christos.gentsos@cern.ch> | 2019-06-06 13:56:18 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-06-06 19:06:03 +0200 |
| commit | 761b344a1cd3018eb5b6b60ea5efc047c199fe23 (patch) | |
| tree | 1dc9768d02eb4b47ce52460b96404ee4af97160b | |
| parent | 235316900770c52304ce572974a1a717d736a09d (diff) | |
| download | ghdl-761b344a1cd3018eb5b6b60ea5efc047c199fe23.tar.gz ghdl-761b344a1cd3018eb5b6b60ea5efc047c199fe23.tar.bz2 ghdl-761b344a1cd3018eb5b6b60ea5efc047c199fe23.zip | |
synth: enabled vector AND, OR and XOR
| -rw-r--r-- | src/synth/synth-expr.adb | 22 |
1 files changed, 14 insertions, 8 deletions
diff --git a/src/synth/synth-expr.adb b/src/synth/synth-expr.adb index 71e1469c1..7299cfe70 100644 --- a/src/synth/synth-expr.adb +++ b/src/synth/synth-expr.adb @@ -423,14 +423,14 @@ package body Synth.Expr is No_Range); end Synth_Bit_Dyadic; - -- function Synth_Vec_Dyadic (Id : Dyadic_Module_Id) return Value_Acc - -- is - -- L : constant Net := Get_Net (Left); - -- begin - -- return Create_Value_Net - -- (Build_Dyadic (Build_Context, Id, L, Get_Net (Right)), - -- Create_Res_Range (Left, L)); - -- end Synth_Vec_Dyadic; + function Synth_Vec_Dyadic (Id : Dyadic_Module_Id) return Value_Acc + is + L : constant Net := Get_Net (Left); + begin + return Create_Value_Net + (Build_Dyadic (Build_Context, Id, L, Get_Net (Right)), + Create_Res_Range (Left, L)); + end Synth_Vec_Dyadic; begin case Def is when Iir_Predefined_Error => @@ -446,6 +446,12 @@ package body Synth.Expr is when Iir_Predefined_Bit_Or | Iir_Predefined_Ieee_1164_Scalar_Or => return Synth_Bit_Dyadic (Id_Or); + when Iir_Predefined_Ieee_1164_Vector_And => + return Synth_Vec_Dyadic (Id_And); + when Iir_Predefined_Ieee_1164_Vector_Or => + return Synth_Vec_Dyadic (Id_Or); + when Iir_Predefined_Ieee_1164_Vector_Xor => + return Synth_Vec_Dyadic (Id_Xor); when Iir_Predefined_Bit_Nor | Iir_Predefined_Ieee_1164_Scalar_Nor => |