synth: handle more signed operations. For #1101

4 files changed, 203 insertions, 153 deletions

diff --git a/python/libghdl/thin/vhdl/nodes.py b/python/libghdl/thin/vhdl/nodes.py
index 140fcb3ab..2d690fd2f 100644
--- a/python/libghdl/thin/vhdl/nodes.py
+++ b/python/libghdl/thin/vhdl/nodes.py
@@ -1202,146 +1202,150 @@ class Iir_Predefined:
     Ieee_Numeric_Std_Sub_Uns_Uns = 219
     Ieee_Numeric_Std_Sub_Uns_Nat = 220
     Ieee_Numeric_Std_Sub_Nat_Uns = 221
-    Ieee_Numeric_Std_Sub_Sgn_Sgn = 222
-    Ieee_Numeric_Std_Sub_Sgn_Int = 223
-    Ieee_Numeric_Std_Sub_Int_Sgn = 224
-    Ieee_Numeric_Std_Mul_Uns_Uns = 225
-    Ieee_Numeric_Std_Mul_Uns_Nat = 226
-    Ieee_Numeric_Std_Mul_Nat_Uns = 227
-    Ieee_Numeric_Std_Mul_Sgn_Sgn = 228
-    Ieee_Numeric_Std_Mul_Sgn_Int = 229
-    Ieee_Numeric_Std_Mul_Int_Sgn = 230
-    Ieee_Numeric_Std_Div_Uns_Uns = 231
-    Ieee_Numeric_Std_Div_Uns_Nat = 232
-    Ieee_Numeric_Std_Div_Nat_Uns = 233
-    Ieee_Numeric_Std_Div_Sgn_Sgn = 234
-    Ieee_Numeric_Std_Div_Sgn_Int = 235
-    Ieee_Numeric_Std_Div_Int_Sgn = 236
-    Ieee_Numeric_Std_Gt_Uns_Uns = 237
-    Ieee_Numeric_Std_Gt_Uns_Nat = 238
-    Ieee_Numeric_Std_Gt_Nat_Uns = 239
-    Ieee_Numeric_Std_Gt_Sgn_Sgn = 240
-    Ieee_Numeric_Std_Gt_Sgn_Int = 241
-    Ieee_Numeric_Std_Gt_Int_Sgn = 242
-    Ieee_Numeric_Std_Lt_Uns_Uns = 243
-    Ieee_Numeric_Std_Lt_Uns_Nat = 244
-    Ieee_Numeric_Std_Lt_Nat_Uns = 245
-    Ieee_Numeric_Std_Lt_Sgn_Sgn = 246
-    Ieee_Numeric_Std_Lt_Sgn_Int = 247
-    Ieee_Numeric_Std_Lt_Int_Sgn = 248
-    Ieee_Numeric_Std_Le_Uns_Uns = 249
-    Ieee_Numeric_Std_Le_Uns_Nat = 250
-    Ieee_Numeric_Std_Le_Nat_Uns = 251
-    Ieee_Numeric_Std_Le_Sgn_Sgn = 252
-    Ieee_Numeric_Std_Le_Sgn_Int = 253
-    Ieee_Numeric_Std_Le_Int_Sgn = 254
-    Ieee_Numeric_Std_Ge_Uns_Uns = 255
-    Ieee_Numeric_Std_Ge_Uns_Nat = 256
-    Ieee_Numeric_Std_Ge_Nat_Uns = 257
-    Ieee_Numeric_Std_Ge_Sgn_Sgn = 258
-    Ieee_Numeric_Std_Ge_Sgn_Int = 259
-    Ieee_Numeric_Std_Ge_Int_Sgn = 260
-    Ieee_Numeric_Std_Eq_Uns_Uns = 261
-    Ieee_Numeric_Std_Eq_Uns_Nat = 262
-    Ieee_Numeric_Std_Eq_Nat_Uns = 263
-    Ieee_Numeric_Std_Eq_Sgn_Sgn = 264
-    Ieee_Numeric_Std_Eq_Sgn_Int = 265
-    Ieee_Numeric_Std_Eq_Int_Sgn = 266
-    Ieee_Numeric_Std_Ne_Uns_Uns = 267
-    Ieee_Numeric_Std_Ne_Uns_Nat = 268
-    Ieee_Numeric_Std_Ne_Nat_Uns = 269
-    Ieee_Numeric_Std_Ne_Sgn_Sgn = 270
-    Ieee_Numeric_Std_Ne_Sgn_Int = 271
-    Ieee_Numeric_Std_Ne_Int_Sgn = 272
-    Ieee_Numeric_Std_Shl_Uns_Nat = 273
-    Ieee_Numeric_Std_Shr_Uns_Nat = 274
-    Ieee_Numeric_Std_Shl_Sgn_Nat = 275
-    Ieee_Numeric_Std_Shr_Sgn_Nat = 276
-    Ieee_Numeric_Std_Sll_Uns_Int = 277
-    Ieee_Numeric_Std_Sll_Sgn_Int = 278
-    Ieee_Numeric_Std_Srl_Uns_Int = 279
-    Ieee_Numeric_Std_Srl_Sgn_Int = 280
-    Ieee_Numeric_Std_Sla_Uns_Int = 281
-    Ieee_Numeric_Std_Sla_Sgn_Int = 282
-    Ieee_Numeric_Std_Sra_Uns_Int = 283
-    Ieee_Numeric_Std_Sra_Sgn_Int = 284
-    Ieee_Numeric_Std_Rol_Uns_Nat = 285
-    Ieee_Numeric_Std_Ror_Uns_Nat = 286
-    Ieee_Numeric_Std_Rol_Sgn_Nat = 287
-    Ieee_Numeric_Std_Ror_Sgn_Nat = 288
-    Ieee_Numeric_Std_Not_Uns = 289
-    Ieee_Numeric_Std_Not_Sgn = 290
-    Ieee_Numeric_Std_And_Uns_Uns = 291
-    Ieee_Numeric_Std_And_Sgn_Sgn = 292
-    Ieee_Numeric_Std_Or_Uns_Uns = 293
-    Ieee_Numeric_Std_Or_Sgn_Sgn = 294
-    Ieee_Numeric_Std_Nand_Uns_Uns = 295
-    Ieee_Numeric_Std_Nand_Sgn_Sgn = 296
-    Ieee_Numeric_Std_Nor_Uns_Uns = 297
-    Ieee_Numeric_Std_Nor_Sgn_Sgn = 298
-    Ieee_Numeric_Std_Xor_Uns_Uns = 299
-    Ieee_Numeric_Std_Xor_Sgn_Sgn = 300
-    Ieee_Numeric_Std_Xnor_Uns_Uns = 301
-    Ieee_Numeric_Std_Xnor_Sgn_Sgn = 302
-    Ieee_Numeric_Std_Neg_Uns = 303
-    Ieee_Numeric_Std_Neg_Sgn = 304
-    Ieee_Numeric_Std_Match_Log = 305
-    Ieee_Numeric_Std_Match_Uns = 306
-    Ieee_Numeric_Std_Match_Sgn = 307
-    Ieee_Numeric_Std_Match_Slv = 308
-    Ieee_Numeric_Std_Match_Suv = 309
-    Ieee_Math_Real_Ceil = 310
-    Ieee_Math_Real_Round = 311
-    Ieee_Math_Real_Log2 = 312
-    Ieee_Math_Real_Sin = 313
-    Ieee_Math_Real_Cos = 314
-    Ieee_Std_Logic_Unsigned_Add_Slv_Slv = 315
-    Ieee_Std_Logic_Unsigned_Add_Slv_Int = 316
-    Ieee_Std_Logic_Unsigned_Add_Int_Slv = 317
-    Ieee_Std_Logic_Unsigned_Add_Slv_Sl = 318
-    Ieee_Std_Logic_Unsigned_Add_Sl_Slv = 319
-    Ieee_Std_Logic_Unsigned_Sub_Slv_Slv = 320
-    Ieee_Std_Logic_Unsigned_Sub_Slv_Int = 321
-    Ieee_Std_Logic_Unsigned_Sub_Int_Slv = 322
-    Ieee_Std_Logic_Unsigned_Sub_Slv_Sl = 323
-    Ieee_Std_Logic_Unsigned_Sub_Sl_Slv = 324
-    Ieee_Std_Logic_Unsigned_Lt_Slv_Slv = 325
-    Ieee_Std_Logic_Unsigned_Lt_Slv_Int = 326
-    Ieee_Std_Logic_Unsigned_Lt_Int_Slv = 327
-    Ieee_Std_Logic_Unsigned_Le_Slv_Slv = 328
-    Ieee_Std_Logic_Unsigned_Le_Slv_Int = 329
-    Ieee_Std_Logic_Unsigned_Le_Int_Slv = 330
-    Ieee_Std_Logic_Unsigned_Gt_Slv_Slv = 331
-    Ieee_Std_Logic_Unsigned_Gt_Slv_Int = 332
-    Ieee_Std_Logic_Unsigned_Gt_Int_Slv = 333
-    Ieee_Std_Logic_Unsigned_Ge_Slv_Slv = 334
-    Ieee_Std_Logic_Unsigned_Ge_Slv_Int = 335
-    Ieee_Std_Logic_Unsigned_Ge_Int_Slv = 336
-    Ieee_Std_Logic_Unsigned_Eq_Slv_Slv = 337
-    Ieee_Std_Logic_Unsigned_Eq_Slv_Int = 338
-    Ieee_Std_Logic_Unsigned_Eq_Int_Slv = 339
-    Ieee_Std_Logic_Unsigned_Ne_Slv_Slv = 340
-    Ieee_Std_Logic_Unsigned_Ne_Slv_Int = 341
-    Ieee_Std_Logic_Unsigned_Ne_Int_Slv = 342
-    Ieee_Std_Logic_Unsigned_Conv_Integer = 343
-    Ieee_Std_Logic_Signed_Add_Slv_Slv = 344
-    Ieee_Std_Logic_Signed_Add_Slv_Int = 345
-    Ieee_Std_Logic_Signed_Add_Int_Slv = 346
-    Ieee_Std_Logic_Signed_Add_Slv_Sl = 347
-    Ieee_Std_Logic_Signed_Add_Sl_Slv = 348
-    Ieee_Std_Logic_Signed_Sub_Slv_Slv = 349
-    Ieee_Std_Logic_Signed_Sub_Slv_Int = 350
-    Ieee_Std_Logic_Signed_Sub_Int_Slv = 351
-    Ieee_Std_Logic_Signed_Sub_Slv_Sl = 352
-    Ieee_Std_Logic_Signed_Sub_Sl_Slv = 353
-    Ieee_Std_Logic_Arith_Conv_Unsigned_Int = 354
-    Ieee_Std_Logic_Arith_Conv_Unsigned_Uns = 355
-    Ieee_Std_Logic_Arith_Conv_Unsigned_Sgn = 356
-    Ieee_Std_Logic_Arith_Conv_Unsigned_Log = 357
-    Ieee_Std_Logic_Arith_Conv_Integer_Int = 358
-    Ieee_Std_Logic_Arith_Conv_Integer_Uns = 359
-    Ieee_Std_Logic_Arith_Conv_Integer_Sgn = 360
-    Ieee_Std_Logic_Arith_Conv_Integer_Log = 361
+    Ieee_Numeric_Std_Sub_Uns_Log = 222
+    Ieee_Numeric_Std_Sub_Log_Uns = 223
+    Ieee_Numeric_Std_Sub_Sgn_Sgn = 224
+    Ieee_Numeric_Std_Sub_Sgn_Int = 225
+    Ieee_Numeric_Std_Sub_Int_Sgn = 226
+    Ieee_Numeric_Std_Sub_Sgn_Log = 227
+    Ieee_Numeric_Std_Sub_Log_Sgn = 228
+    Ieee_Numeric_Std_Mul_Uns_Uns = 229
+    Ieee_Numeric_Std_Mul_Uns_Nat = 230
+    Ieee_Numeric_Std_Mul_Nat_Uns = 231
+    Ieee_Numeric_Std_Mul_Sgn_Sgn = 232
+    Ieee_Numeric_Std_Mul_Sgn_Int = 233
+    Ieee_Numeric_Std_Mul_Int_Sgn = 234
+    Ieee_Numeric_Std_Div_Uns_Uns = 235
+    Ieee_Numeric_Std_Div_Uns_Nat = 236
+    Ieee_Numeric_Std_Div_Nat_Uns = 237
+    Ieee_Numeric_Std_Div_Sgn_Sgn = 238
+    Ieee_Numeric_Std_Div_Sgn_Int = 239
+    Ieee_Numeric_Std_Div_Int_Sgn = 240
+    Ieee_Numeric_Std_Gt_Uns_Uns = 241
+    Ieee_Numeric_Std_Gt_Uns_Nat = 242
+    Ieee_Numeric_Std_Gt_Nat_Uns = 243
+    Ieee_Numeric_Std_Gt_Sgn_Sgn = 244
+    Ieee_Numeric_Std_Gt_Sgn_Int = 245
+    Ieee_Numeric_Std_Gt_Int_Sgn = 246
+    Ieee_Numeric_Std_Lt_Uns_Uns = 247
+    Ieee_Numeric_Std_Lt_Uns_Nat = 248
+    Ieee_Numeric_Std_Lt_Nat_Uns = 249
+    Ieee_Numeric_Std_Lt_Sgn_Sgn = 250
+    Ieee_Numeric_Std_Lt_Sgn_Int = 251
+    Ieee_Numeric_Std_Lt_Int_Sgn = 252
+    Ieee_Numeric_Std_Le_Uns_Uns = 253
+    Ieee_Numeric_Std_Le_Uns_Nat = 254
+    Ieee_Numeric_Std_Le_Nat_Uns = 255
+    Ieee_Numeric_Std_Le_Sgn_Sgn = 256
+    Ieee_Numeric_Std_Le_Sgn_Int = 257
+    Ieee_Numeric_Std_Le_Int_Sgn = 258
+    Ieee_Numeric_Std_Ge_Uns_Uns = 259
+    Ieee_Numeric_Std_Ge_Uns_Nat = 260
+    Ieee_Numeric_Std_Ge_Nat_Uns = 261
+    Ieee_Numeric_Std_Ge_Sgn_Sgn = 262
+    Ieee_Numeric_Std_Ge_Sgn_Int = 263
+    Ieee_Numeric_Std_Ge_Int_Sgn = 264
+    Ieee_Numeric_Std_Eq_Uns_Uns = 265
+    Ieee_Numeric_Std_Eq_Uns_Nat = 266
+    Ieee_Numeric_Std_Eq_Nat_Uns = 267
+    Ieee_Numeric_Std_Eq_Sgn_Sgn = 268
+    Ieee_Numeric_Std_Eq_Sgn_Int = 269
+    Ieee_Numeric_Std_Eq_Int_Sgn = 270
+    Ieee_Numeric_Std_Ne_Uns_Uns = 271
+    Ieee_Numeric_Std_Ne_Uns_Nat = 272
+    Ieee_Numeric_Std_Ne_Nat_Uns = 273
+    Ieee_Numeric_Std_Ne_Sgn_Sgn = 274
+    Ieee_Numeric_Std_Ne_Sgn_Int = 275
+    Ieee_Numeric_Std_Ne_Int_Sgn = 276
+    Ieee_Numeric_Std_Shl_Uns_Nat = 277
+    Ieee_Numeric_Std_Shr_Uns_Nat = 278
+    Ieee_Numeric_Std_Shl_Sgn_Nat = 279
+    Ieee_Numeric_Std_Shr_Sgn_Nat = 280
+    Ieee_Numeric_Std_Sll_Uns_Int = 281
+    Ieee_Numeric_Std_Sll_Sgn_Int = 282
+    Ieee_Numeric_Std_Srl_Uns_Int = 283
+    Ieee_Numeric_Std_Srl_Sgn_Int = 284
+    Ieee_Numeric_Std_Sla_Uns_Int = 285
+    Ieee_Numeric_Std_Sla_Sgn_Int = 286
+    Ieee_Numeric_Std_Sra_Uns_Int = 287
+    Ieee_Numeric_Std_Sra_Sgn_Int = 288
+    Ieee_Numeric_Std_Rol_Uns_Nat = 289
+    Ieee_Numeric_Std_Ror_Uns_Nat = 290
+    Ieee_Numeric_Std_Rol_Sgn_Nat = 291
+    Ieee_Numeric_Std_Ror_Sgn_Nat = 292
+    Ieee_Numeric_Std_Not_Uns = 293
+    Ieee_Numeric_Std_Not_Sgn = 294
+    Ieee_Numeric_Std_And_Uns_Uns = 295
+    Ieee_Numeric_Std_And_Sgn_Sgn = 296
+    Ieee_Numeric_Std_Or_Uns_Uns = 297
+    Ieee_Numeric_Std_Or_Sgn_Sgn = 298
+    Ieee_Numeric_Std_Nand_Uns_Uns = 299
+    Ieee_Numeric_Std_Nand_Sgn_Sgn = 300
+    Ieee_Numeric_Std_Nor_Uns_Uns = 301
+    Ieee_Numeric_Std_Nor_Sgn_Sgn = 302
+    Ieee_Numeric_Std_Xor_Uns_Uns = 303
+    Ieee_Numeric_Std_Xor_Sgn_Sgn = 304
+    Ieee_Numeric_Std_Xnor_Uns_Uns = 305
+    Ieee_Numeric_Std_Xnor_Sgn_Sgn = 306
+    Ieee_Numeric_Std_Neg_Uns = 307
+    Ieee_Numeric_Std_Neg_Sgn = 308
+    Ieee_Numeric_Std_Match_Log = 309
+    Ieee_Numeric_Std_Match_Uns = 310
+    Ieee_Numeric_Std_Match_Sgn = 311
+    Ieee_Numeric_Std_Match_Slv = 312
+    Ieee_Numeric_Std_Match_Suv = 313
+    Ieee_Math_Real_Ceil = 314
+    Ieee_Math_Real_Round = 315
+    Ieee_Math_Real_Log2 = 316
+    Ieee_Math_Real_Sin = 317
+    Ieee_Math_Real_Cos = 318
+    Ieee_Std_Logic_Unsigned_Add_Slv_Slv = 319
+    Ieee_Std_Logic_Unsigned_Add_Slv_Int = 320
+    Ieee_Std_Logic_Unsigned_Add_Int_Slv = 321
+    Ieee_Std_Logic_Unsigned_Add_Slv_Sl = 322
+    Ieee_Std_Logic_Unsigned_Add_Sl_Slv = 323
+    Ieee_Std_Logic_Unsigned_Sub_Slv_Slv = 324
+    Ieee_Std_Logic_Unsigned_Sub_Slv_Int = 325
+    Ieee_Std_Logic_Unsigned_Sub_Int_Slv = 326
+    Ieee_Std_Logic_Unsigned_Sub_Slv_Sl = 327
+    Ieee_Std_Logic_Unsigned_Sub_Sl_Slv = 328
+    Ieee_Std_Logic_Unsigned_Lt_Slv_Slv = 329
+    Ieee_Std_Logic_Unsigned_Lt_Slv_Int = 330
+    Ieee_Std_Logic_Unsigned_Lt_Int_Slv = 331
+    Ieee_Std_Logic_Unsigned_Le_Slv_Slv = 332
+    Ieee_Std_Logic_Unsigned_Le_Slv_Int = 333
+    Ieee_Std_Logic_Unsigned_Le_Int_Slv = 334
+    Ieee_Std_Logic_Unsigned_Gt_Slv_Slv = 335
+    Ieee_Std_Logic_Unsigned_Gt_Slv_Int = 336
+    Ieee_Std_Logic_Unsigned_Gt_Int_Slv = 337
+    Ieee_Std_Logic_Unsigned_Ge_Slv_Slv = 338
+    Ieee_Std_Logic_Unsigned_Ge_Slv_Int = 339
+    Ieee_Std_Logic_Unsigned_Ge_Int_Slv = 340
+    Ieee_Std_Logic_Unsigned_Eq_Slv_Slv = 341
+    Ieee_Std_Logic_Unsigned_Eq_Slv_Int = 342
+    Ieee_Std_Logic_Unsigned_Eq_Int_Slv = 343
+    Ieee_Std_Logic_Unsigned_Ne_Slv_Slv = 344
+    Ieee_Std_Logic_Unsigned_Ne_Slv_Int = 345
+    Ieee_Std_Logic_Unsigned_Ne_Int_Slv = 346
+    Ieee_Std_Logic_Unsigned_Conv_Integer = 347
+    Ieee_Std_Logic_Signed_Add_Slv_Slv = 348
+    Ieee_Std_Logic_Signed_Add_Slv_Int = 349
+    Ieee_Std_Logic_Signed_Add_Int_Slv = 350
+    Ieee_Std_Logic_Signed_Add_Slv_Sl = 351
+    Ieee_Std_Logic_Signed_Add_Sl_Slv = 352
+    Ieee_Std_Logic_Signed_Sub_Slv_Slv = 353
+    Ieee_Std_Logic_Signed_Sub_Slv_Int = 354
+    Ieee_Std_Logic_Signed_Sub_Int_Slv = 355
+    Ieee_Std_Logic_Signed_Sub_Slv_Sl = 356
+    Ieee_Std_Logic_Signed_Sub_Sl_Slv = 357
+    Ieee_Std_Logic_Arith_Conv_Unsigned_Int = 358
+    Ieee_Std_Logic_Arith_Conv_Unsigned_Uns = 359
+    Ieee_Std_Logic_Arith_Conv_Unsigned_Sgn = 360
+    Ieee_Std_Logic_Arith_Conv_Unsigned_Log = 361
+    Ieee_Std_Logic_Arith_Conv_Integer_Int = 362
+    Ieee_Std_Logic_Arith_Conv_Integer_Uns = 363
+    Ieee_Std_Logic_Arith_Conv_Integer_Sgn = 364
+    Ieee_Std_Logic_Arith_Conv_Integer_Log = 365
 
 Get_Kind = libghdl.vhdl__nodes__get_kind
 Get_Location = libghdl.vhdl__nodes__get_location
diff --git a/src/synth/synth-oper.adb b/src/synth/synth-oper.adb
index 754975c0b..a5dc07679 100644
--- a/src/synth/synth-oper.adb
+++ b/src/synth/synth-oper.adb
@@ -325,10 +325,13 @@ package body Synth.Oper is
          L1, R1 : Net;
          N : Net;
       begin
+         Rtype := Left.Typ;
+         if Rtype.Kind = Type_Vector then
+            Rtype := Rtype.Vec_El;
+         end if;
+
          if Is_Res_Vec then
-            Rtype := Create_Vec_Type_By_Length (W, Left.Typ.Vec_El);
-         else
-            Rtype := Left.Typ;
+            Rtype := Create_Vec_Type_By_Length (W, Rtype);
          end if;
          L1 := Synth_Sresize (Left, W, Expr);
          R1 := Synth_Sresize (Right, W, Expr);
@@ -375,6 +378,18 @@ package body Synth.Oper is
          return Create_Value_Net (N, Create_Res_Bound (Left));
       end Synth_Dyadic_Sgn_Int;
 
+      function Synth_Dyadic_Int_Sgn (Id : Dyadic_Module_Id) return Value_Acc
+      is
+         R : constant Net := Get_Net (Right);
+         L1 : Net;
+         N : Net;
+      begin
+         L1 := Synth_Sresize (Left, Right.Typ.W, Expr);
+         N := Build_Dyadic (Build_Context, Id, R, L1);
+         Set_Location (N, Expr);
+         return Create_Value_Net (N, Create_Res_Bound (Right));
+      end Synth_Dyadic_Int_Sgn;
+
       function Synth_Compare_Sgn_Sgn (Id : Compare_Module_Id)
                                      return Value_Acc
       is
@@ -506,7 +521,12 @@ package body Synth.Oper is
          when Iir_Predefined_Ieee_Numeric_Std_Add_Sgn_Int =>
             --  "+" (Signed, Integer)
             return Synth_Dyadic_Sgn_Int (Id_Add);
-         when Iir_Predefined_Ieee_Numeric_Std_Add_Sgn_Sgn =>
+         when Iir_Predefined_Ieee_Numeric_Std_Add_Int_Sgn =>
+            --  "+" (Integer, Signed)
+            return Synth_Dyadic_Int_Sgn (Id_Add);
+         when Iir_Predefined_Ieee_Numeric_Std_Add_Sgn_Sgn
+           | Iir_Predefined_Ieee_Numeric_Std_Add_Sgn_Log
+           | Iir_Predefined_Ieee_Numeric_Std_Add_Log_Sgn =>
             --  "+" (Signed, Signed)
             return Synth_Dyadic_Sgn (Id_Add, True);
 
@@ -523,7 +543,12 @@ package body Synth.Oper is
            | Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Slv_Int =>
             --  "-" (Signed, Integer)
             return Synth_Dyadic_Sgn_Int (Id_Sub);
-         when Iir_Predefined_Ieee_Numeric_Std_Sub_Sgn_Sgn =>
+         when Iir_Predefined_Ieee_Numeric_Std_Sub_Int_Sgn =>
+            --  "-" (Integer, Signed)
+            return Synth_Dyadic_Int_Sgn (Id_Sub);
+         when Iir_Predefined_Ieee_Numeric_Std_Sub_Sgn_Sgn
+           | Iir_Predefined_Ieee_Numeric_Std_Sub_Sgn_Log
+           | Iir_Predefined_Ieee_Numeric_Std_Sub_Log_Sgn =>
             --  "-" (Signed, Signed)
             return Synth_Dyadic_Sgn (Id_Sub, True);
 
@@ -564,7 +589,7 @@ package body Synth.Oper is
                L1 := Synth_Uresize (Left, W, Expr);
                R1 := Synth_Uresize (Right, W, Expr);
                Rtype := Create_Vec_Type_By_Length (W, Left.Typ.Vec_El);
-               N := Build_Dyadic (Build_Context, Id_Umul, L1, R1);
+               N := Build_Dyadic (Ctxt, Id_Umul, L1, R1);
                Set_Location (N, Expr);
                return Create_Value_Net (N, Rtype);
             end;
@@ -580,9 +605,26 @@ package body Synth.Oper is
                L1 := Synth_Uresize (Left, W, Expr);
                R1 := Synth_Uresize (Right, W, Expr);
                Rtype := Create_Vec_Type_By_Length (Lw, Left.Typ.Vec_El);
+               N := Build_Dyadic (Ctxt, Id_Udiv, L1, R1);
+               Set_Location (N, Expr);
+               N := Build2_Uresize (Ctxt, N, Lw, Get_Location (Expr));
+               return Create_Value_Net (N, Rtype);
+            end;
+
+         when Iir_Predefined_Ieee_Numeric_Std_Div_Sgn_Int =>
+            declare
+               Lw : constant Width := Left.Typ.W;
+               W : constant Width := Width'Max (Lw, Right.Typ.W);
+               L1, R1 : Net;
+               Rtype : Type_Acc;
+               N : Net;
+            begin
+               L1 := Synth_Sresize (Left, W, Expr);
+               R1 := Synth_Sresize (Right, W, Expr);
+               Rtype := Create_Vec_Type_By_Length (Lw, Left.Typ.Vec_El);
                N := Build_Dyadic (Build_Context, Id_Udiv, L1, R1);
                Set_Location (N, Expr);
-               N := Synth_Uresize (N, Lw, Expr);
+               N := Build2_Sresize (Ctxt, N, Lw, Get_Location (Expr));
                return Create_Value_Net (N, Rtype);
             end;
 
diff --git a/src/vhdl/vhdl-ieee-numeric.adb b/src/vhdl/vhdl-ieee-numeric.adb
index 2bb43e1f8..9b93ffacc 100644
--- a/src/vhdl/vhdl-ieee-numeric.adb
+++ b/src/vhdl/vhdl-ieee-numeric.adb
@@ -52,8 +52,8 @@ package body Vhdl.Ieee.Numeric is
            (Arg_Vect_Vect => Iir_Predefined_Ieee_Numeric_Std_Add_Sgn_Sgn,
             Arg_Vect_Scal => Iir_Predefined_Ieee_Numeric_Std_Add_Sgn_Int,
             Arg_Scal_Vect => Iir_Predefined_Ieee_Numeric_Std_Add_Int_Sgn,
-            Arg_Vect_Log  => Iir_Predefined_None,
-            Arg_Log_Vect  => Iir_Predefined_None)),
+            Arg_Vect_Log  => Iir_Predefined_Ieee_Numeric_Std_Add_Sgn_Log,
+            Arg_Log_Vect  => Iir_Predefined_Ieee_Numeric_Std_Add_Log_Sgn)),
       Pkg_Bit =>
         (others =>
            (others => Iir_Predefined_None)));
@@ -64,14 +64,14 @@ package body Vhdl.Ieee.Numeric is
            (Arg_Vect_Vect => Iir_Predefined_Ieee_Numeric_Std_Sub_Uns_Uns,
             Arg_Vect_Scal => Iir_Predefined_Ieee_Numeric_Std_Sub_Uns_Nat,
             Arg_Scal_Vect => Iir_Predefined_Ieee_Numeric_Std_Sub_Nat_Uns,
-            Arg_Vect_Log  => Iir_Predefined_None,
-            Arg_Log_Vect  => Iir_Predefined_None),
+            Arg_Vect_Log  => Iir_Predefined_Ieee_Numeric_Std_Sub_Uns_Log,
+            Arg_Log_Vect  => Iir_Predefined_Ieee_Numeric_Std_Sub_Log_Uns),
          Type_Signed =>
            (Arg_Vect_Vect => Iir_Predefined_Ieee_Numeric_Std_Sub_Sgn_Sgn,
             Arg_Vect_Scal => Iir_Predefined_Ieee_Numeric_Std_Sub_Sgn_Int,
             Arg_Scal_Vect => Iir_Predefined_Ieee_Numeric_Std_Sub_Int_Sgn,
-            Arg_Vect_Log  => Iir_Predefined_None,
-            Arg_Log_Vect  => Iir_Predefined_None)),
+            Arg_Vect_Log  => Iir_Predefined_Ieee_Numeric_Std_Sub_Sgn_Log,
+            Arg_Log_Vect  => Iir_Predefined_Ieee_Numeric_Std_Sub_Log_Sgn)),
       Pkg_Bit =>
         (others =>
            (others => Iir_Predefined_None)));
diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads
index ca02854fc..0f9a4c213 100644
--- a/src/vhdl/vhdl-nodes.ads
+++ b/src/vhdl/vhdl-nodes.ads
@@ -5489,9 +5489,13 @@ package Vhdl.Nodes is
       Iir_Predefined_Ieee_Numeric_Std_Sub_Uns_Uns,
       Iir_Predefined_Ieee_Numeric_Std_Sub_Uns_Nat,
       Iir_Predefined_Ieee_Numeric_Std_Sub_Nat_Uns,
+      Iir_Predefined_Ieee_Numeric_Std_Sub_Uns_Log,
+      Iir_Predefined_Ieee_Numeric_Std_Sub_Log_Uns,
       Iir_Predefined_Ieee_Numeric_Std_Sub_Sgn_Sgn,
       Iir_Predefined_Ieee_Numeric_Std_Sub_Sgn_Int,
       Iir_Predefined_Ieee_Numeric_Std_Sub_Int_Sgn,
+      Iir_Predefined_Ieee_Numeric_Std_Sub_Sgn_Log,
+      Iir_Predefined_Ieee_Numeric_Std_Sub_Log_Sgn,
 
       Iir_Predefined_Ieee_Numeric_Std_Mul_Uns_Uns,
       Iir_Predefined_Ieee_Numeric_Std_Mul_Uns_Nat,