testsuite/gna: add a test for #2424

3 files changed, 78 insertions, 0 deletions

diff --git a/testsuite/gna/issue2424/ent.vhdl b/testsuite/gna/issue2424/ent.vhdl
new file mode 100644
index 000000000..b163b474c
--- /dev/null
+++ b/testsuite/gna/issue2424/ent.vhdl
@@ -0,0 +1,32 @@
+package pkg is
+	type rec is record
+		elem : bit_vector;
+	end record;
+
+	type arr is array(natural range <>) of rec;
+end package;
+
+use work.pkg.all;
+
+entity e is
+	port (
+		p : in arr
+	);
+end entity;
+
+architecture a of e is
+	signal sig : p'subtype;
+begin
+
+end architecture;
+
+entity top is
+end top;
+
+use work.pkg.all;
+
+architecture behav of top is
+  signal s : arr (1 to 4)(elem(7 downto 0));
+begin
+  dut : entity work.e port map (p => s);
+end behav;
diff --git a/testsuite/gna/issue2424/ent2.vhdl b/testsuite/gna/issue2424/ent2.vhdl
new file mode 100644
index 000000000..72baff12e
--- /dev/null
+++ b/testsuite/gna/issue2424/ent2.vhdl
@@ -0,0 +1,32 @@
+package pkg2 is
+	type rec is record
+		elem : bit_vector;
+	end record;
+
+	type arr is array(natural range <>) of rec;
+end package;
+
+use work.pkg2.all;
+
+entity e2 is
+	port (
+		p : in rec
+	);
+end entity;
+
+architecture a of e2 is
+	signal sig : p'subtype;
+begin
+
+end architecture;
+
+entity top2 is
+end top2;
+
+use work.pkg2.all;
+
+architecture behav of top2 is
+  signal s : rec (elem(7 downto 0));
+begin
+  dut : entity work.e2 port map (p => s);
+end behav;
diff --git a/testsuite/gna/issue2424/testsuite.sh b/testsuite/gna/issue2424/testsuite.sh
new file mode 100755
index 000000000..db3352bb8
--- /dev/null
+++ b/testsuite/gna/issue2424/testsuite.sh
@@ -0,0 +1,14 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+analyze ent.vhdl
+elab_simulate top
+
+analyze ent2.vhdl
+elab_simulate top2
+
+clean
+
+echo "Test successful"