simul: add debug command 'run -s'

3 files changed, 18 insertions, 8 deletions

diff --git a/src/simul/simul-vhdl_debug.adb b/src/simul/simul-vhdl_debug.adb
index 11bd17f43..33ffdb798 100644
--- a/src/simul/simul-vhdl_debug.adb
+++ b/src/simul/simul-vhdl_debug.adb
@@ -754,16 +754,22 @@ package body Simul.Vhdl_Debug is
    procedure Run_Proc (Line : String)
    is
       Delta_Time : Std_Time;
-      P : Positive;
+      P, L : Positive;
    begin
       P := Skip_Blanks (Line);
       if P <= Line'Last then
-         Delta_Time := Grt.Options.Parse_Time (Line (P .. Line'Last));
-         if Delta_Time = -1 then
-            return;
+         L := Get_Word (Line, P);
+         if Line (P .. L) = "-s" then
+            Simul.Vhdl_Simul.Break_Step := True;
+         else
+            Delta_Time := Grt.Options.Parse_Time (Line (P .. L));
+            if Delta_Time = -1 then
+               --  Error, ignore command.
+               return;
+            end if;
+            Simul.Vhdl_Simul.Break_Time := Current_Time + Delta_Time;
+            Grt.Processes.Next_Time := Current_Time + Delta_Time;
          end if;
-         Simul.Vhdl_Simul.Break_Time := Current_Time + Delta_Time;
-         Grt.Processes.Next_Time := Current_Time + Delta_Time;
       end if;
 
       Elab.Debugger.Prepare_Continue;
diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb
index 82342b599..2a330d472 100644
--- a/src/simul/simul-vhdl_simul.adb
+++ b/src/simul/simul-vhdl_simul.adb
@@ -4040,6 +4040,7 @@ package body Simul.Vhdl_Simul is
       Status : Integer;
    begin
       Break_Time := Std_Time'Last;
+      Break_Step := False;
 
       Grt.Options.Progname := To_Ghdl_C_String (Ghdl_Progname'Address);
       Grt.Errors.Set_Error_Stream (Grt.Stdio.stdout);
@@ -4092,11 +4093,13 @@ package body Simul.Vhdl_Simul is
               or Status = Grt.Errors.Run_Stop
               or Status = Grt.Errors.Run_Finished;
 
-            if Current_Time >= Break_Time
-              and then Break_Time /= Std_Time'Last
+            if Break_Step
+              or else (Current_Time >= Break_Time
+                         and then Break_Time /= Std_Time'Last)
             then
                --  No not break anymore on time,
                Break_Time := Std_Time'Last;
+               Break_Step := False;
                Elab.Debugger.Debug_Time;
             end if;
 
diff --git a/src/simul/simul-vhdl_simul.ads b/src/simul/simul-vhdl_simul.ads
index 66a032f22..47c1273be 100644
--- a/src/simul/simul-vhdl_simul.ads
+++ b/src/simul/simul-vhdl_simul.ads
@@ -33,6 +33,7 @@ with Grt.Signals;
 
 package Simul.Vhdl_Simul is
    Break_Time : Std_Time;
+   Break_Step : Boolean;
 
    Trace_Simulation : Boolean := False;