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| author | Tristan Gingold <tgingold@free.fr> | 2021-02-04 08:14:34 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2021-02-04 08:15:59 +0100 |
| commit | 8e58f10787a209cadb18699b47fc9b127121440a (patch) | |
| tree | 598069cb244e106ac2f70b6580d088b2d4521696 | |
| parent | 3c7ad475444f5ad8075df9127a80f83879ae71dd (diff) | |
| download | ghdl-8e58f10787a209cadb18699b47fc9b127121440a.tar.gz ghdl-8e58f10787a209cadb18699b47fc9b127121440a.tar.bz2 ghdl-8e58f10787a209cadb18699b47fc9b127121440a.zip | |
synth: handle to_stdlogicvector. For #1628
| -rw-r--r-- | src/synth/synth-static_oper.adb | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/synth/synth-static_oper.adb b/src/synth/synth-static_oper.adb index bcaadbb0c..8190b5ba8 100644 --- a/src/synth/synth-static_oper.adb +++ b/src/synth/synth-static_oper.adb @@ -845,7 +845,8 @@ package body Synth.Static_Oper is end; when Iir_Predefined_Ieee_Numeric_Std_Touns_Nat_Nat_Uns - | Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Int => + | Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Int + | Iir_Predefined_Ieee_Numeric_Std_Unsigned_To_Slv_Nat_Nat_Slv => return Eval_To_Vector (Uns64 (Read_Discrete (Param1)), Read_Discrete (Param2), Res_Typ); |