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| author | Tristan Gingold <tgingold@free.fr> | 2023-03-09 18:43:09 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2023-03-09 18:43:09 +0100 |
| commit | 93754b34f0d154aa3aa39a86fcc914dc8daa9630 (patch) | |
| tree | 2ea66d6d1d9e14b6666ad6fcda44687b2e9fad7b | |
| parent | e82c258ec20e9261cf9b76cbaa2e60ab33d61d9a (diff) | |
| download | ghdl-93754b34f0d154aa3aa39a86fcc914dc8daa9630.tar.gz ghdl-93754b34f0d154aa3aa39a86fcc914dc8daa9630.tar.bz2 ghdl-93754b34f0d154aa3aa39a86fcc914dc8daa9630.zip | |
synth: support selected signal assignment
| -rw-r--r-- | src/synth/synth-vhdl_stmts.adb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/synth/synth-vhdl_stmts.adb b/src/synth/synth-vhdl_stmts.adb index 4fae9b5a8..9a8e0e36a 100644 --- a/src/synth/synth-vhdl_stmts.adb +++ b/src/synth/synth-vhdl_stmts.adb @@ -3951,6 +3951,8 @@ package body Synth.Vhdl_Stmts is Synth_Simple_Signal_Assignment (C.Inst, Stmt); when Iir_Kind_Conditional_Signal_Assignment_Statement => Synth_Conditional_Signal_Assignment (C.Inst, Stmt); + when Iir_Kind_Selected_Waveform_Assignment_Statement => + Synth_Selected_Signal_Assignment (C.Inst, Stmt); when Iir_Kind_Variable_Assignment_Statement => Synth_Variable_Assignment (C.Inst, Stmt); when Iir_Kind_Conditional_Variable_Assignment_Statement => |