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author | Tristan Gingold <tgingold@free.fr> | 2020-02-17 18:41:55 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-02-17 18:41:55 +0100 |
commit | 939221749e7f1228ed959d1007a3fd3e3b4b9146 (patch) | |
tree | fa7441c3c77fc2e7e9db986dd95eed2ebebc154d | |
parent | f8a4d339538d5abdaf9f6e29107816c247d5d39f (diff) | |
download | ghdl-939221749e7f1228ed959d1007a3fd3e3b4b9146.tar.gz ghdl-939221749e7f1228ed959d1007a3fd3e3b4b9146.tar.bz2 ghdl-939221749e7f1228ed959d1007a3fd3e3b4b9146.zip |
testsuite/gna: add tests for previous commit.
-rw-r--r-- | testsuite/gna/bug0110/tb.vhdl | 34 | ||||
-rw-r--r-- | testsuite/gna/bug0110/tb2.vhdl | 25 | ||||
-rw-r--r-- | testsuite/gna/bug0110/tb3.vhdl | 34 | ||||
-rw-r--r-- | testsuite/gna/bug0110/tb4.vhdl | 31 | ||||
-rw-r--r-- | testsuite/gna/bug0110/tb5.vhdl | 31 | ||||
-rwxr-xr-x | testsuite/gna/bug0110/testsuite.sh | 13 |
6 files changed, 168 insertions, 0 deletions
diff --git a/testsuite/gna/bug0110/tb.vhdl b/testsuite/gna/bug0110/tb.vhdl new file mode 100644 index 000000000..c62c44545 --- /dev/null +++ b/testsuite/gna/bug0110/tb.vhdl @@ -0,0 +1,34 @@ +package pkg is + type my_rec is record + adr : bit_vector (7 downto 0); + end record; +end pkg; + +use work.pkg.all; + +entity ent is + port (v : out my_rec; + b : in bit); +end ent; + +architecture behav of ent is +begin + v.adr <= (others => b); +end behav; + +entity top is +end top; + +use work.pkg.all; +architecture behav of top is + signal s : bit_vector (7 downto 0); + signal b : bit; +begin + dut : entity work.ent + port map ( + -- ERROR: missing 1 downto 0! + v.adr (3 downto 2) => s (3 downto 2), + v.adr (7 downto 4) => s (7 downto 4), + b => b); + b <= '0'; +end behav; diff --git a/testsuite/gna/bug0110/tb2.vhdl b/testsuite/gna/bug0110/tb2.vhdl new file mode 100644 index 000000000..b0c54eeb9 --- /dev/null +++ b/testsuite/gna/bug0110/tb2.vhdl @@ -0,0 +1,25 @@ +entity ent2 is + port (v : out bit_vector (7 downto 0); + b : in bit); +end ent2; + +architecture behav of ent2 is +begin + v <= (others => b); +end behav; + +entity top2 is +end top2; + +architecture behav of top2 is + signal s : bit_vector (7 downto 0); + signal b : bit; +begin + dut : entity work.ent2 + port map ( + -- ERROR: missing 1 downto 0! + v (3 downto 2) => s (3 downto 2), + v (7 downto 4) => s (7 downto 4), + b => b); + b <= '0'; +end behav; diff --git a/testsuite/gna/bug0110/tb3.vhdl b/testsuite/gna/bug0110/tb3.vhdl new file mode 100644 index 000000000..9cc894275 --- /dev/null +++ b/testsuite/gna/bug0110/tb3.vhdl @@ -0,0 +1,34 @@ +package pkg3 is + type my_rec is record + adr : bit_vector (7 downto 0); + end record; +end pkg3; + +use work.pkg3.all; + +entity ent3 is + port (v : out my_rec; + b : in bit); +end ent3; + +architecture behav of ent3 is +begin + v.adr <= (others => b); +end behav; + +entity top3 is +end top3; + +use work.pkg3.all; +architecture behav of top3 is + signal s : bit_vector (7 downto 0); + signal b : bit; +begin + dut : entity work.ent3 + port map ( + -- ERROR: missing 1 downto 0! + v.adr (3 downto 2) => s (3 downto 2), + v.adr (7 downto 6) => s (7 downto 6), + b => b); + b <= '0'; +end behav; diff --git a/testsuite/gna/bug0110/tb4.vhdl b/testsuite/gna/bug0110/tb4.vhdl new file mode 100644 index 000000000..54b9b8a62 --- /dev/null +++ b/testsuite/gna/bug0110/tb4.vhdl @@ -0,0 +1,31 @@ +package pkg4 is + type my_arr is array (1 to 2) of bit_vector (7 downto 0); +end pkg4; + +use work.pkg4.all; + +entity ent4 is + port (v : out my_arr; + b : in bit); +end ent4; + +architecture behav of ent4 is +begin + v <= (others => (others => b)); +end behav; + +entity top4 is +end top4; + +use work.pkg4.all; +architecture behav of top4 is + signal s : bit_vector (7 downto 0); + signal b : bit; +begin + dut : entity work.ent4 + port map ( + v(1)(3 downto 2) => s (3 downto 2), + v(2)(7 downto 6) => s (7 downto 6), + b => b); + b <= '0'; +end behav; diff --git a/testsuite/gna/bug0110/tb5.vhdl b/testsuite/gna/bug0110/tb5.vhdl new file mode 100644 index 000000000..76706e44d --- /dev/null +++ b/testsuite/gna/bug0110/tb5.vhdl @@ -0,0 +1,31 @@ +package pkg_5 is + type my_arr is array (natural range <>) of bit_vector (7 downto 0); +end pkg_5; + +use work.pkg_5.all; + +entity ent_5 is + port (v : out my_arr; + b : in bit); +end ent_5; + +architecture behav of ent_5 is +begin + v (1) <= (others => b); +end behav; + +entity top_5 is +end top_5; + +use work.pkg_5.all; +architecture behav of top_5 is + signal s : bit_vector (7 downto 0); + signal b : bit; +begin + dut : entity work.ent_5 + port map ( + v(1)(3 downto 2) => s (3 downto 2), + v(2)(7 downto 6) => s (7 downto 6), + b => b); + b <= '0'; +end behav; diff --git a/testsuite/gna/bug0110/testsuite.sh b/testsuite/gna/bug0110/testsuite.sh new file mode 100755 index 000000000..ad9ecf367 --- /dev/null +++ b/testsuite/gna/bug0110/testsuite.sh @@ -0,0 +1,13 @@ +#! /bin/sh + +. ../../testenv.sh + +analyze_failure tb2.vhdl +analyze_failure tb.vhdl +analyze_failure tb3.vhdl +analyze_failure tb4.vhdl +analyze_failure tb5.vhdl + +clean + +echo "Test successful" |