synth: add a test for wait statement.

3 files changed, 58 insertions, 1 deletions

diff --git a/testsuite/synth/dff01/dff11.vhdl b/testsuite/synth/dff01/dff11.vhdl
new file mode 100644
index 000000000..568eb79d4
--- /dev/null
+++ b/testsuite/synth/dff01/dff11.vhdl
@@ -0,0 +1,17 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity dff11 is
+  port (q : out std_logic_vector(7 downto 0);
+        d : std_logic_vector(7 downto 0);
+        clk : std_logic);
+end dff11;
+
+architecture behav of dff11 is
+begin
+  process
+  begin
+    wait until rising_edge (clk);
+    q <= d;
+  end process;
+end behav;
diff --git a/testsuite/synth/dff01/tb_dff11.vhdl b/testsuite/synth/dff01/tb_dff11.vhdl
new file mode 100644
index 000000000..a1bb443e4
--- /dev/null
+++ b/testsuite/synth/dff01/tb_dff11.vhdl
@@ -0,0 +1,40 @@
+entity tb_dff11 is
+end tb_dff11;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_dff11 is
+  signal clk : std_logic;
+  signal din : std_logic_vector (7 downto 0);
+  signal dout : std_logic_vector (7 downto 0);
+begin
+  dut: entity work.dff11
+    port map (
+      q => dout,
+      d => din,
+      clk => clk);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    din <= x"00";
+    pulse;
+    assert dout = x"00" severity failure;
+    din <= x"ab";
+    pulse;
+    assert dout = x"ab" severity failure;
+    pulse;
+    assert dout = x"ab" severity failure;
+    din <= x"12";
+    pulse;
+    assert dout = x"12" severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/dff01/testsuite.sh b/testsuite/synth/dff01/testsuite.sh
index 1e0f0631c..7f52a9acd 100755
--- a/testsuite/synth/dff01/testsuite.sh
+++ b/testsuite/synth/dff01/testsuite.sh
@@ -2,7 +2,7 @@
 
 . ../../testenv.sh
 
-for t in dff01 dff02 dff03 dff04 dff05 dff06 dff07 dff08 dff09 dff10; do
+for t in dff01 dff02 dff03 dff04 dff05 dff06 dff07 dff08 dff09 dff10 dff11; do
     analyze $t.vhdl tb_$t.vhdl
     elab_simulate tb_$t
     clean